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publication number s29vs_xs-r_00 revision 03 issue date september 12, 2008 s29vs/xs-r mirrorbit ? flash family s29vs/xs-r mirrorbit ? flash family cover sheet s29vs256r, s29vs128r, s29xs256r, s29xs128r 256/128 mb (16/8 m x 16 bit) 1.8 v burst simu ltaneous read/write, multiplexed mirrorbit flash memory data sheet (advance information) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document contains information on one or more products under development at spansion inc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed pr oduct without notice. publication number s29vs_xs-r_00 revision 03 issue date september 12, 2008 features ? single 1.8 v read/program/erase (1.70?1.95 v) ? 65 nm mirrorbit technology ? address and data interface options ? address and data multiplexed for reduced i/o count (adm) s29vs-r ? address-high, address-low, data multiplexed for minimum i/o count (aadm) s29xs-r ? simultaneous read/write operation ? 32-word write buffer ? bank architecture ? eight-bank (vs256/128r) ? four 32-kb sectors at the top or bottom of memory array (vs256/128r) ? 255/127 of 128-kb sectors (vs256/128r) ? programmable linear (8/16) with wrap around and continuous burst read modes ? secured silicon sector region consisting of 128 words each for factory and customer ? 10-year data retention (typical) ? cycling endurance: 100,000 cycles per sector (typical) ? rdy output indicates data available to system ? command set compatible with jedec (42.4) standard ? hardware sector protection via v pp pin ? handshaking by monitoring rdy ? offered packages ? 44-ball fbga (6.2 mm x 7.7 mm x 1.0 mm) ? low v cc write inhibit ? write operation status bits indicate program and erase operation completion ? suspend and resume commands for program and erase operations ? asynchronous program operation, independent of burst control register settings ? v pp input pin to reduce factory programming time ? support for common flash interface (cfi) general description the spansion s29vs256/128r and s29xs256/128r are mirrorbit ? flash products fabricated on 65 nm process technology. these burst mode flash devices are capable of performing simu ltaneous read and write operations with zero latency on two separate banks using multiplexed data and address pins. these products can operate up to 104 mhz and use a single v cc of 1.7 v to 1.95 v that makes them ideal for the demanding wireless applications of today that r equire higher density, better performance, and lowered power consumption. the s29vs256/ 128r operates in adm mode, while the s29xs256/128r can operate in the aadm mode. performance characteristics s29vs/xs-r mirrorbit ? flash family s29vs256r, s29vs128r, s29xs256r, s29xs128r 256/128 mb (16/8 m x 16 bit) 1.8 v burst simu ltaneous read/write, multiplexed mirrorbit flash memory data sheet (advance information) read access times speed option (mhz) 104 max. synch. latency, ns (t iacc) 75 max. synch. burst access, ns (t bacc) 7.6 max. asynch. access time, ns (t acc )80 max oe# access time, ns (t oe )15 current consumption (typical values) continuous burst read @ 104 mhz 32 ma simultaneous operation @ 66 mhz 50 ma program/erase 20 ma standby mode 20 a typical program & erase times single word programming 130 s effective write buffer programming (v cc ) per word 9.4 s effective write buffer programming (v pp ) per word 4.8 s sector erase (16 kword sector) 350 ms sector erase (64 kword sector) 600 ms
4 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. input/output descrip tions & logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. physical dimensions/connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 special handling instructions for fbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. address space maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 data address & quantity nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 flash memory array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 address/data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 device id and cfi (id-cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7. device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 synchronous (burst) read mode and configuration regi ster. . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4 blank check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.5 simultaneous read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.6 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.7 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.8 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.9 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.10 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8. sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 sector lock/unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2 sector lock range command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3 hardware data protection methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.4 ssr lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.5 secure silicon region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9. power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.4 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.5 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.6 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.7 v cc power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.8 clk characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.9 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11. appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.1 command definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.2 device id and common flash memory interface addre ss map . . . . . . . . . . . . . . . . . . . . . . 62 12. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 5 data sheet (advance information) figures figure 3.1 simultaneous operation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4.1 44-ball very thin fine-pitch ball grid array, top view, balls facing down . . . . . . . . . . . . . 10 figure 4.2 vdj044?44-ball very thin fine-pitch ball grid array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7.1 synchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 10.2 maximum positive overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 figure 10.3 input pulse and test point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 10.4 output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 10.5 v cc power-up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 10.6 clk characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10.7 synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 10.8 asynchronous mode read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 10.9 asynchronous program operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 figure 10.10 reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 10.11 latency with boundary crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 10.12 latency with boundary crossing into bank performing embedded operation . . . . . . . . . . . 56 figure 10.13 example of programmable wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 10.14 back-to-back read/write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 11.1 asynchronous read - aadm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 11.2 asynchronous read followed by read - aadm interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 11.3 asynchronous read followed by write - aadm interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 11.4 asynchronous write - aadm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 11.5 asynchronous write followed by read - aadm interface . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 11.6 asynchronous write followed by write - aadm interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 11.7 synchronous read wrapped burst address low only - aadm interface . . . . . . . . . . . . . . .70 figure 11.8 synchronous read continuous bu rst - aadm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 11.9 synchronous read wrapped burst - aadm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 11.10 synchronous write followed by read burst - aadm interface . . . . . . . . . . . . . . . . . . . . . .71 figure 11.11 synchronous read followed by write - aadm interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 11.12 synchronous write followed by read burst - aadm interface . . . . . . . . . . . . . . . . . . . . . . .72 figure 11.13 synchronous write followed by write - aadm interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) tables table 2.1 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 6.1 system versus flash view of address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 6.2 s29vs/xs256r sector and memory address map (top boot) . . . . . . . . . . . . . . . . . . . . . . .16 table 6.3 s29vs/xs256r sector and memory address map (bottom boot) . . . . . . . . . . . . . . . . . . . . .16 table 6.4 s29vs/xs128r sector and memory address map (top boot) . . . . . . . . . . . . . . . . . . . . . . .17 table 6.5 s29vs/xs128r sector and memory address map (bottom boot) . . . . . . . . . . . . . . . . . . . . .17 table 6.6 device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 6.7 id-cfi address map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 6.8 secured silicon region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 7.1 wait state vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 7.2 address latency for 10 -13 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 7.3 address latency for 9 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 7.4 address latency for 8 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7.5 address latency for 7 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7.6 address latency for 6 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7.7 address latency for 5 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7.8 address latency for 4 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 7.9 address latency for 3 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 7.10 burst address groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 7.11 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 7.12 status register reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 7.13 status register - bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 7.14 status register - bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 7.15 status register - bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 7.16 status register - bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 7.17 status register - bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 7.18 status register - bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 7.19 status register - bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 7.20 status register - bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 7.21 write buffer program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 7.22 program suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 7.23 program resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 7.24 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 7.25 chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 7.26 erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 7.27 erase resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 7.28 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 8.1 secured silicon region entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 8.2 secured silicon region program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 8.3 secured silicon region exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 10.1 v cc power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 10.2 warm-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 11.1 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 11.2 id/cfi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 7 data sheet (advance information) 1. ordering information the ordering part number is formed by a valid combination of the following: 1.1 valid combinations valid combination list configurations are planned to be suppo rted in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading s29 and packing type designator from ordering part number. s29vs 256 r xx bh w 00 0 packing type 0 = tray (standard; see note ( note 1 )) 3 = 13-inch tape and reel model number 00 = top 01 = bottom temperature range w = wireless (?25c to +85c) package type and material bh = very thin fine-pitch bga, low halogen lead (pb)-free package speed option (burst frequency) 0p = 66 mhz 0s = 83 mhz ab = 104 mhz process technology r = 65 nm mirrorbit ? te c h n o l o gy flash density 256 = 256 mb 128 = 128 mb device family s29vs256r =1.8 volt-only simultaneous read/write, burst-mode address and data multiplexed flash memory s29xs256r =1.8 volt-only simultaneous read/write, burst-mode address low, address high and data multiplexed flash memory s29vs-r valid combinations (1) (2) model numbers package type (2) base ordering part number speed option package type, material, and temperature range packing type s29vs256r 0p, 0s, ab bhw low halogen lead (pb)-free 0, 3 (1) 00, 01 6.2 mm x 7.7 mm, 44-ball s29vs128r s29xs256r s29xs128r
8 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 2. input/output descriptions & logic symbol table 2.1 identifies the input and output packa ge connections provided on the device. table 2.1 input/output descriptions symbol type description amax ? a16 higher order address lines. amax = a23 for vs256r, a22 for vs128r. on the xs256r and xs128r, these inputs can be left unconnected in aadm mode. a/dq15 ? a/dq0 i/o multiplexe d address/data input/output ce# input flash chip enable. asynchronous relative to clk. oe# input output enable. asynchronous relative to clk for the burst mode. we# input write enable v cc supply device power supply v ccq supply input/output power supply (must be ramped simultaneously with v cc ) v ss i/o ground v ssq i/o input/output ground nc no connect no connected internally rdy output ready. indicates when valid burst data is ready to be read clk input the first rising edge of clk in conjunction with avd# low latches address input and activates burst mode operation. after the initial word is output, subsequent rising edges of clk increment the internal address counter. clk should remain low during asynchronous access avd# input address valid input. indicates to device that the valid address is present on the address inputs (address bits a15 ? a0 are multiplexed, address bits amax ? a16 are address only). v il = for asynchronous mode, indicates valid address; for burst mode, cause staring address to be latched on rising edge of clk. v ih = device ignores address inputs reset# input hardware reset. low = device resets and returns to reading array data. v pp input accelerated input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il ,disables all program and erase functions. should be at v ih for all other conditions. rfu reserved reserved for future use
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 9 data sheet (advance information) 3. block diagrams figure 3.1 simultaneous operation circuit notes: 1. amax = a23 for s29vs/xs256r, a22 for s29vs/xs128r. 2. bank(n) = 8 (s29vs/xs256/128r). v ss v cc bank address reset# vpp we# ce# avd# rdy dq15?dq0 state control & command register bank 1 x-decoder y-decoder latches and control logic bank 0 x-decoder y-decoder latches and control logic dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 bank (n-1) y-decoder x-decoder latches and control logic bank (n) y-decoder x-decoder latches and control logic oe# status control amax?a0 amax?a0 amax?a0 amax?a0 bank address bank address bank address v ssq
10 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 4. physical dimensions/connection diagrams this section shows the i/o designations and package specifications for the s29vs-r. 4.1 related documents the following documents contain information relating to the s29vs-r devices. click on the title or go to www.spansion.com , or request a copy from your sales office. ? considerations for x-ray inspection of su rface-mounted flash integrated circuits 4.2 special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150c for prolonged periods of time. 4.2.1 44-ball very thin fine-pitch ba ll grid array, s29vs256r/s29xs256r/ s29vs128r/s29xs128r figure 4.1 44-ball very thin fine-pitch ball grid array, top view, balls facing down notes 1. ball d7 is nc for s29vs128r. 2. balls d7, c12, c4, d5, c10, d10, c11, d4 are nc for s29xs256r and s29xs128r 3 2910 5 47 68 1 13 12 14 11 nc nc b d e f g h a c rdy vpp a19 vss a21 vcc clk we# a22 a17 vccq nc a18 a20 a16 a23 avd# reset# vssq ce# vss a/dq2 a/dq9 a/dq6 a/dq7 a/dq12 a/dq13 a/dq3 oe# a/dq8 a/dq15 a/dq10 vccq vssq a/dq14 a/dq4 a/dq5 a/dq11 a/dq0 a/dq1 nc nc
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 11 data sheet (advance information) 4.2.2 vdj044-44-ball very thin fine-pitc h ball grid array, 6.2mm x 7.7 mm figure 4.2 vdj044?44-ball very thin fine-pitch ball grid array 3616 \ 16-039.27 \ 12.5.6 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vdj 044 jedec n/a 7.70 mm x 6.20 mm nom package symbol min nom max note a 0.86 0.93 1.00 overall thickness a1 0.18 0.23 0.28 ball height a2 0.64 0.71 0.78 body thickness d 7.60 7.70 7.80 body size e 6.10 6.20 6.30 body size d1 4.50 bsc. ball footprint e1 1.50 bsc. ball footprint md 10 row matrix size d direction me 4 row matrix size e direction n 44 total ball count ? b 0.25 0.30 0.35 ball diameter e 0.50 bsc. ball pitch sd / se 0.25 bsc. solder ball placement depopulated solder balls
12 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 5. product overview the s29vs/xs-r family is 1.8-v only, simultaneous read/write, burst-mode, flas h devices. these devices have a 16 bit (word) wide data bus. a ll read accesses provide 16 bits of data on each bus transfer cycle. all writes take 16 bits of data from each bus transfer cycle. the flash memory array is divided into banks. a bank is the address range within which one program, or erase operation may be in progress at the same time as one read operation is in progress in any other bank of the memory. this multiple bank structure enables simultaneous read and write (srw) so that code may be executed or data read from one bank while a group of data is programmed, or erased as a background task in one other bank. each bank is divided into sectors. a sector is the mi nimum address range of data which can be erased to an all ones state. most of the sectors are 128-kbytes ea ch. depending on the option ordered, either the top-4 sectors or the bottom-4 sectors are 32-kbytes each. these are called boot sectors because they are often used for holding boot code or paramet ers that need to be protected or eras ed separately from other data in the flash array. programming is done via a 64 byte write buffer. it is possible to program from one to 32 words (64 bytes) in each programming operation. the s29vs/xs family is capable of continuous, syn chronous (burst) read or linear read (8- or 16-word aligned group) with wrap around. a wr apped burst begins at the initial location and continues to the end of an 8, or 16-word aligned group then ?wraps-around? to c ontinue at the beginning of the 8, or 16-word aligned group. the burst completes with the la st word before the initial location . word wrap around burst is generally used for processor cache line fill. device mbits mbytes mwords banks mbytes / bank s29vs128r/s29xs129r 128 16 8 8 2 s29vs256r/s29xs256r 256 32 16 8 4
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 13 data sheet (advance information) 6. address space maps there are five address spaces within each device: ? a non-volatile flash memory array used for storage of data that may be randomly accessed by asynchronous or burst read operations. ? a read only memory array used for factory programmed permanent device characteristics information. this area contains the device identification (i d) and common flash interface (cfi) information. ? a one time programmable (otp) non-volatile flash array used for factory programmed permanent data, and customer programmable perm anent data. this is called the secure silicon region (ssr). ? an otp location used to permanently protect the ssr. this is call the ssr lock. ? a volatile register used to configure device behavior options. this is called the configuration register. the main flash memory array is the primary and default address space but, it may be partially overlaid by the other four address spaces with one al ternate address space available at any one time. the location where the alternate address space is overlaid is defined by th e address provided in the command that enables each overlay. the portion of the command address that is suffici ent to select a sector is used to select the sector that is overlaid by an alter nate address space overlay (aso). any address range, within the overlaid sector, not defined by an overlay addr ess map, is reserved for future use. all read accesses outside of an address map wit hin the selected sector, return non-valid data. the locations will display actively driven data but the meanin g of whatever ones or zeros appear are not defined. there are three operation modes for each bank that determine what portions of the address space are readable at any given time: ? read mode ? embedded algorithm (ea) mode ? address space overlay (aso) mode each bank of the device can be in any operation mode but, only one bank can be in ea or aso mode at any one time. in read mode, a flash memory array bank may be directly read by asynchronous or burst accesses from the host system bus. the control unit (cu) puts all ban ks in read mode during power-on, a hardware reset, after a command reset, or after a bank is returned to read mode from ea mode. in ea mode the flash memory array data in a bank is stable but undefined, and effectively unavailable for read access from the host system. while in ea mode the bank is used by the cu in the execution of commands. typical ea mode operations are programming or erasing of data in the flash array. all other banks are available for read access while the one bank is in ea mode. this ability to read from one bank while another bank is used in the execution of a command is called si multaneous read and write (srw) and allows for continued operation of the system via the r eading of data or execution of code from other banks while one bank is programming or erasing data as a relatively long time frame background task. in aso mode, one of the overlay address spaces are over laid in a bank (entered). that bank is in aso mode and no other bank may be in ea or aso mode. all ea ac tivity must be complete d before entering any aso mode. a command for entering an ea or aso mode wh ile another bank is in ea or aso mode will be ignored. while an aso mode is active (entered) in a bank, a r ead for flash array data to any other bank is allowed. aso mode selects a specific sector for the overlaid address space. other sectors in the aso bank still provide flash array data and may be read during aso mode. the asos are functionally tied to the lowest address bank. the comma nds used to overlay (enter) these areas must select a sector addre ss within the lowest address bank. while ssr lock, ssr, or configuration register is ov erlaid only the ssr lock, ssr, or configuration register respectively may be programmed in the over laid sector. while any of these aso areas are being programmed the aso bank switches to ea mode. the id/cfi and factor y portion of the ssr aso is not customer programmable. the address nomenclature used in this document is a shorthand form that shows addresses are formed from a concatenation of high order bits, su fficient to select a sector address (sa), with low order bits to select a location within the sector. when in read mode and reading from the flash array the entire address is used to
14 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) select a specific word for asynchronous read or the starting word address of a burst read. when writing a command, the address bits between sa and the command s pecified least significant bits must be zero to allow for future extension of an overlay address map. 6.1 data address & quantity nomenclature a bit is a single one or zero data value. a byte is a gr oup of 8 bits aligned on an 8 bit boundary. a word is a group of 16 bits aligned on a 16 bit boundary. throughout this document quantities of data are generally ex pressed in terms of byte units . example: most sectors have 128 kilo bytes of data and is written as 128 kbytes or 128kb. addresses are also expressed in byte units . a 128 kbyte sector has an address range from 00000h to 1ffffh byte locations. byte units are used because most host systems and software for these systems use byte resolution addresses. software & hardware developers most often ca lculate code and data sizes in terms of bytes, so this is more familiar terminology than describing data si zes in bits or words. in general, data units will not be abbreviated if possible so that full unit names of by te, word, or bit are used. however, there may be cases where capital b is used for byte units and lower case b is used for bit units, in situations where space is limited such as in table column headers. in some cases data quantities will also be expressed in word or bit units in addition to the quantity shown in bytes. this may be done as an aid to readers familia r with prior device generation documentation which often provided only word or bit unit values. word units may also be used to emphasize that, in the memory devices described in this documentation, data is always exchanged with the host system in word units. each bus cycle transfer of read or write data on the host system bus is a transfer 16 bits of data. a read bus cycle is always a16 bit wide transfer of data to the host system whether the host system chooses to look at all the bits or not. a write bus cycle is always a transfer of 16 bi ts to the memory device and the device will store all 16 bits to a register. in the case of a program operation all 16 bits of each word to be programmed will be stored in the flash array. because data is always transferred in word units, t he memory devices being discussed use only the address signals from the system necessary to select words. the host system byte address uses system address a0 to select bytes and a1 to select words. flash memories wi th word wide data paths have traditionally started their address signal numbering with a0 being the selector fo r words because a byte select input is not needed. so, system address a-maximum to a1 are connected to flas h a-maximum to a0 (the documentation convention here is to use lower case for system address signal nu mbering and u pper case for flash address signals). in prior generation flash documentation, address values used in commands to the flash were documented from the viewpoint of the flash device - the bit pattern appearing on flash address inputs a10 to a0. however, most software is written with addresses expressed in bytes. this means the address patterns shown in flash command tables have traditionally be en shifted by one bit to express them as byte address values in flash control programs. example: a prior generation flash data sheet would show a command write of data value xxa0h to address 555h; this is an address pattern of 10101010101b on flash address inputs a10 to a0; but software would define this as a byte address value of aaah since the least significant address bit is not used by the flash); which is 101010101010b on system address bus a11 to a0. because system a11 to a1 is connected to flash a10 to a0 the flash word address of 555h and the system byte address of aaah provides the same bit pattern on the same address inputs. because all address values are being documented as system byte addresses, that are more familiar to softw are writers, the command ta bles have addresses that are shifted from those shown in prior generation devices.
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 15 data sheet (advance information) 6.2 flash memory array the non-volatile flash memory array is organized as shown in the following tables. devices are factory configured to have either all uniform size sectors or f our smaller sectors at either the top of the device. table 6.1 system versus flash view of address system address signals a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 system byte address hex aaa binary pattern 101010101010 flash word address hex 55 5 flash address signals a10a9a8a7a6a5a4a3a2a1a0
16 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) note: all tables have been condensed to show sector-related information for an entire device on a single page. sectors and their addr ess ranges that are not explicitly listed (such as sa008?sa009) have sector starting and ending addresses that form the same pattern as al l other sectors of that size. for example, all 128 kb se ctors have the byte address pattern x000000h?x1ffffh. note all tables have been condensed to show sector-related information for an entire device on a single page. sectors and their addr ess ranges that are not explicitly listed (such as sa008?sa009) have sector starting and ending addresses that form the same pattern as al l other sectors of that size. for example, all 128 kb se ctors have the byte address pattern x000000h?x1ffffh. table 6.2 s29vs/xs256r sector and memory address map (top boot) bank size (mbit) sector count sector size (kbyte) bank sector range address range (word) address range (byte) notes 32 224 128 0 sa000-sa031 000000h?1fffffh 000000h?3fffffh sector starting address ? sector ending address 1 sa032?sa063 ? ? 2 sa064?sa095 ? ? 3 sa096?sa127 ? ? 4 sa128?sa159 ? ? 5 sa160?sa191 ? ? 6 sa192?sa223 ? ? 31 128 7 sa224?sa254 e00000h?feffffh 1c00000h?1fdffffh 432 sa255 ff0000h?ff3fffh 1fe0000h?1fe7fffh sa256 ff4000h-ff7fffh 1fe8000h-1feffffh sa257 ff8000h?ffbfffh 1ff0000h?1ff7fffh sa258 ffc000h?ffffffh 1ff8000h?1ffffffh table 6.3 s29vs/xs256r sector and memory address map (bottom boot) bank size (mbit) sector count sector size (kbyte) bank sector range address range (word) address range (byte) notes 32 432 0 sa000 000000h?003fffh 000000h?007fffh sector starting address ? sector ending address sa001 004000h?007fffh 008000h?00ffffh sa002 008000h?00bfffh 010000h?017fffh sa003 00c000h?00ffffh 018000h?01ffffh 31 128 sa004?sa034 010000h?1fffffh 020000h?3fffffh 224 128 1 sa035?sa066 ? ? 2 sa067?sa098 ? ? 3 sa099?sa130 ? ? 4 sa131?sa162 ? ? 5 sa163?sa194 ? ? 6 sa195?sa226 ? ? 7 sa227?sa258 e00000h?ffffffh 1c00000h?1ffffffh
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 17 data sheet (advance information) note all tables have been condensed to show sector-related information for an entire device on a single page. sectors and their addr ess ranges that are not explicitly listed (such as sa008?sa009) have sector starting and ending addresses that form the same pattern as al l other sectors of that size. for example, all 128 kb se ctors have the byte address pattern x000000h?x1ffffh. note all tables have been condensed to show sector-related information for an entire device on a single page. sectors and their addr ess ranges that are not explicitly listed (such as sa008?sa009) have sector starting and ending addresses that form the same pattern as al l other sectors of that size. for example, all 128 kb se ctors have the byte address pattern x000000h?x1ffffh. table 6.4 s29vs/xs128r sector and memory address map (top boot) bank size (mbit) sector count sector size (kbyte) bank sector range address range (word) address range (byte) notes 16 112 128 0 sa000-sa015 000000h?0fffffh 000000h?1fffffh sector starting address ? sector ending address 1 sa016?sa031 ? ? 2 sa032?sa047 ? ? 3 sa048?sa063 ? ? 4 sa064?sa079 ? ? 5 sa080?sa095 ? ? 6 sa096?sa111 ? ? 15 128 7 sa112?sa126 700000h?7effffh e00000h?fdffffh 432 sa127 7f0000h?7f3fffh fe0000h?fe7fffh sa128 7f4000h-7f7fffh fe8000h-feffffh sa129 7f8000h?7fbfffh ff0000h?ff7fffh sa130 7fc000h?7fffffh ff8000h?ffffffh table 6.5 s29vs/xs128r sector and memory address map (bottom boot) bank size (mbit) sector count sector size (kbyte) bank sector range address range (word) address range (byte) notes 16 432 0 sa000 000000h?003fffh 000000h?007fffh sector starting address ? sector ending address sa001 004000h?007fffh 008000h?00ffffh sa002 008000h?00bfffh 010000h?017fffh sa003 00c000h?00ffffh 018000h?01ffffh 15 128 sa004?sa018 010000h?0fffffh 020000h?1fffffh 112 128 1 sa019?sa034 ? ? 2 sa035?sa050 ? ? 3 sa051?sa066 ? ? 4 sa067?sa082 ? ? 5 sa083?sa098 ? ? 6 sa099?sa114 ? ? 7 sa115?sa130 700000h?7fffffh e00000h?ffffffh
18 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 6.3 address/data interface there are two options for connection to the address and data buses. ? address and data multiplexed (adm) mode. on the s29vs-r devices, the upper address is supplied on separate signal inputs and the lower 16-bits of address are multiplexed with 16-bit data on the a/dq15 to a/dq0 i/os. ? address-high, address-low, and data multiplexed (a adm) mode. on the s20xs-r devices, the upper and lower address are multiplexed with 16-bit data on the a/dq15 to a/d0 signal i/os. the two options allow use with the traditional address/da ta multiplexed nor interface (s29ns family), or an address multiplexed/data multiplexed interface with the lowest signal count. 6.3.1 adm interface (s 29vs256r and s29vs128r) a number of processors use adm interface as a way to reduce pin count. the system permanently connects the upper address bits (a[max:16] to the device. when avd# is low it connects a[15:0] to dq[15:0]. the address is latched on the rising edge of avd#. when avd# is high, the system connects the data bus to dq[15:0]. this results in 16-pin savings from the traditional interface. 6.3.2 aadm interface (s 29xs256r and s29xs128r) signal input and output (i/o) connections on a high co mplexity component such as an application specific integrated circuit (asic) are a limite d resource. reducing signal count on any interface of the asic allows for either more features or lower package cost. the memory interface described in this section is intended to reduce the i/o signal count associated with the flash memory interface with an asic. the interface is called address-high, address-low, and data multiplexed (aadm) because all address and data information is time multiplexed on a single 16-bit wide bus. this interface is electrically compatible with existing adm 16-bit wide random access static memory interfaces but uses fewer address signals. in that sense aadm is a signal count subset of existing stat ic memory interfaces. this interface can be implemented in existing memory controller designs, as an additional mode, with minimal changes. no new i/o technology is needed and existing memory interfaces can continue to be supported while the electronics industry adopts this new interface. asic designers can reuse the existing memory address signals above a15 for other functions when an aadm memory is in use. by breaking up the memory address in to two time slots the address is naturally extended to be a 32-bit word address. but, using two bus cycles to transfer the address increases initia l access latency by increasing the time address is using the bus. ho wever, many memory accesses are to locations in memory nearby the previous access. very often it is not necessary to provide both cycles of address. this interface stores the high half of address in the memory so that if the high half of address do es not change from the previous access, only the low half of address needs to be sent on the bus. if a new upper address is not captured at the beginning of an access the last captured value of t he upper address is used. this allows accesses within the same 128-kbyte address range to provide only the lower address as part of each access. in aadm mode two signal rising edges are needed to capture the upper and lower address portions in asynchronous mode or two signal combinations over two clocks is needed in synchronous mode. in asynchronous mode the upper address is captured by an avd# rising edge when oe# is low; the lower address is captured on the rising edge of avd# with oe# high. in synchronous mode the upper address is captured at the rising clock edge when avd# and oe# are low; the lower address is captured at the rising edge of clock when avd# is low and oe# is high. ce# going high at any time during the access or oe# returning high after rdy is first asserted high during an access, terminates the read access and causes the ad dress/data bus direction to switch back to input mode. the address/data bus di rection switches from input to output mode only after an address-low capture when avd# is low and oe# is high. this prevents the assertion of oe# during address-high capture from causing a bus conflict between the host address and me mory data signals. note, in burst mode, this implies at least one cycle of ce# or oe# hig h before an address-high for a new a ccess may be placed on the bus so that there is time for the memory to recognize the end of the previous access, stop driving data outputs, and ignore oe# so that assertion of oe# with the new addr ess-high does not create a bus conflict with a new address being driven on the bus. at high bus frequencie s more than one cycle may be need in order to allow time for data outputs to stop driving and new address to be driven (bus turn around time). during a write access, the address/data bus direction is always in the input mode.
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 19 data sheet (advance information) the upper address is set to zero or all ones, for bottom or top boot respectively, during a hardware reset, operate in adm mode during the early phase of boot code ex ecution where only a si ngle address cycle would be issued with the lower 16 bit of the address reac hing the memory in aadm mode. the default high order address bits will direct the early boot accesses to the 128 kbytes at the boot end of the device. note that in aadm interface mode this effectively requires that one of t he boot sectors is selected for any address overlay mode because in the initial phase of aadm mode operati on the host memory controller may only issue the low order address thus limiting the early boot time ad dress space to the 128 kbytes at the boot end of the device. 6.3.3 default access mode upon power-up or hardware reset, the device defaults to the asynchronous access mode.
20 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 6.4 bus operations table 6.6 describes the required state of each input signal for each bus operation. legend l = logic 0, h = logic 1, x = can be either v il or v ih . = rising edge. notes 1. data is delivered by a read operation only after the burst initial wait state count has been satisfied. table 6.6 device bus operations operation ce# oe# we# clk avd# a28-a16 a/dq 15-a/dq0 reset# standby & reset standby (ce# deselect) h x x x x x high-z h hardware reset x x x x x x high-z l asynchronous mode operations asynchronous address latch (s29vs256r and s29vs128r) l h x x addr in addr in h asynchronous upper address latch (s29xs256r and s29xs128r only) l l h x x addr in h asynchronous lower address latch (s29xs256r and s29xs128r only) l h x x x addr in h asynchronous read l l h x h x data input valid h asynchronous write latched data l h x h x data input valid h synchronous mode operations latch starting burst address by clk - adm mode l h h l addr in addr in h latch upper starting burst address by clk (s29xs256r and s29xs128r only) l l h l x addr in h latch lower starting burst address by clk (s29xs256r and s29xs128r only) l h h l x addr in h burst read and advance to next address (1) l l h h x data output valid h terminate current burst cycle x x x x x high-z h
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 21 data sheet (advance information) 6.5 device id and cfi (id-cfi) there are two tr aditional methods fo r systems to identify the type of fl ash memory installed in the system. one has been traditionally been called autoselect and is now referred to as device identification (id). a command is used to enable an address space overlay where up to 16 word locations can be read to get jedec manufacturer identification (id), device id, and so me configuration and protection status information from the flash memory. the system ca n use the manufacturer and device id s to select the appropriate driver software to use with the flash device. the other method is called common flash interface (cfi). it also uses a command to enable an address space overlay where an extendable table of st andard information about how the flash memory is organized and behaves can be re ad. with this method the driver software does not have to be written with the specifics of each possible memory device in mind. instead the driver software is written in a more general way to handle many different devices but adjusts the dr iver behavior based on the information in the cf i table stored in the flash memory. tradit ionally these two address spaces have used separate commands and were separate overlays. ho wever, the mapping of these two address spaces are non-overlapping and so can be combined in to a single address space and appear together in a single overlay. either of the traditional commands used to ac cess (enter) the autoselect (id) or cfi overlay will cause the now combined id-cfi address map to appear. a write at any sector address, in bank zero, having t he least significant byte address value of aah, with xx98h or xx90h data, switches the addressed sector to an over lay of the id-cfi address map. these are called id- cfi enter commands and are only valid when written to the specified bank when it is in read mode. the id- cfi address map appears within, and replaces flash a rray data of, the selected sector address range. the id-cfi enter commands use the same address and dat a values used on previous generation memories to access the jedec manufacturer id (autoselect) and common flash interface (cfi) information, respectively. while the id-cfi address space is overlaid , any write with xxf0h data to the device will remove the overlay and return the selected sector to showi ng flash memory array data. thus, the id-cfi address space and commands are backward compatible with standard memory discovery algorithms. within the id-cfi address map there are two subsections: for the complete address map see tables in section 11.2, device id and common flash memory interface address map on page 62 . 6.5.1 jedec device id the joint electron device engineering council (jedec ) standard jep106t defines a method for reading the manufacturer id and device id of a compliant memory. th is information is primarily intended for programming equipment to automatically match a device with the corresponding programming algorithm. the jedec id information is structur ed to work with any memory data bu s width e.g. x8, x 16, x32. the code values are always byte wide but are located at bus width address boundaries such that incrementing the device address inputs will read successive byte, word, or double word locations with the codes always located in the least significant byte location of the da ta bus. because the data bus is word wide each code byte is located in the lower half of each word location and the high order byte is always zero. table 6.7 id-cfi address map overview byte address description size allocated (bytes) read/write (sa) + 00000h to 0001fh jedec id (traditional autoselect values) 32 read only (sa) + 00020h to ceh h cfi data structure 174 read only
22 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 6.5.2 common flash memory interface the common flash interface (cfi) specif ication defines a standardized data structure that may be read from a flash memory device, which allows vendor-specified so ftware algorithms to be used for entire families of devices. the data structure contains information for sy stem configuration such as various electrical and timing parameters, and special functions supported by the device. software support can then be device- independent, jedec id-independent, and forward-and-backw ard-compatible for the specified flash device families. the system can read cfi informat ion at the addresses within the selected sector as shown in section 11.2, device id and common flash memory interface address map on page 62 . like the jedec device id information, cfi information is structured to work with any memory data bus width e.g. x8, x16, x32. the code values are always byte wide but are located at data bus width address boundaries such that incrementing the device address reads successive byte, word, or double word locations with the codes always located in the least significant byte locati on of the data bus. because the data bus is word wide each code byte is located in the lower half of each word location and the high order byte is always zero. for further information, please refer to the spansion cfi version 1.4 (or later) specification and the spansion cfi publication 100 (see also jedec publications jep137-a and jesd68.01). please contact jedec (http:/ /www.jedec.org) for their standards and the spansion cfi publications may be found at the spansion web site ( http://www.spansion.com/cfi_ v1.4_vendorspec_ext_a0.pdf at the time of this document?s publication). 6.5.3 secured silicon region the secured silicon region provides an extra flas h memory area that can be programmed once and permanently protected from further c hanges. the secured silicon region is 512 bytes in length. it consists of 256 bytes for factory data and 256 bytes for customer-secured data. the secured silicon region (ssr) is overlaid in th e sector address specified by the ssr enter command. 6.5.4 configuration register the configuration register enter command is only valid when written to a bank that is in read mode. the configuration register mode address map appears withi n, and replaces flash array data of, the selected sector address range. the m eaning of the configuration register bits is defined in the configuration register operation description. in configuration register mode, a wr ite of 00f0h to any address will return the sector to read mode. table 6.8 secured silicon region byte address range secure silicon region size (sa) + 0000h to 00ffh factory 256 bytes (sa) + 0100h to 01ffh customer 256 bytes
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 23 data sheet (advance information) 7. device operations this section describes the read and write bus oper ations, program, erase, simultaneous read/write, handshaking, and reset features of the flash devices. the address space of the flash memory array is divi ded into banks. there are three operation modes for each bank: ? read mode ? embedded algorithm (ea) mode ? address space overlay (aso) mode each bank of the device can be in any operation mode but, only one bank can be in ea or aso mode at any one time. in read mode a flash memory array bank may be read by simply selecting the memory, supplying the address, and taking read data when it is ready. this is done by asynchronous or burst accesses from the host system bus. the cu puts all banks in read mode during power-on, a hardware reset, after a command reset, or after a bank is returned to read mode from ea mode. during a burst read access valid read data is indicated by the rdy signal being high. when rdy is low burst read data is not valid and wait states must be added. the use of the rdy signal to indicate when valid data is transferred on the system data bus is call ed handshaking or flow control. ea and aso modes are initiated by writing specific addr ess and data patterns into command registers (see table 11.1 on page 60 ). the command registers do not occupy any memory locations; they are loaded by write bus cycles with the a ddress and data information needed to ex ecute a command. the contents of the registers serve as input to the cont rol unit (cu) and the cu dictates the function of the device. writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return all banks to read mode. the flash memory array data in a bank that is in ea mode, is stable but undefined, and effectively unavailable for read access from the host system. while in ea mode the bank is used by the cu in the execution of commands. typical command operations are programming or erasing of data in the flash array. all other banks are available for read access while the o ne bank is in ea mode. this ability to read from one bank while another bank is used in the execution of a command is called simultaneous read and write (srw) and allows for continued operation of the system via the reading of data or code from other banks while one bank is programming or erasing data as a rela tively long time frame background task. only a status register read command can be used in a bank in ea mode to retrieve the ea status. while any one of the overlay address spaces are overlaid in a bank (entered) that bank is in aso mode and no other bank may be in ea or aso mode. all ea activi ty must be completed or suspended before entering any aso mode. a command for entering an ea or aso mode while another bank is in ea or aso mode will be ignored. while an aso mode is active (entered) in a bank, a r ead for flash array data to any other bank is allowed. aso mode selects a specific sector for the overlaid address space. other sectors in the aso bank still provide flash array data and may be read during aso mode. while ssr lock, ssr, or configuration register is ov erlaid only the ssr lock, ssr, or configuration register respectively may be programmed in the over laid sector. while any of these aso areas are being programmed the aso bank switches to ea mode. the id/cfi and factor y portion of the ssr aso is not customer programmable. an attempt to program in these areas will fail.
24 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 7.1 asynchronous read to read data from the memory array, the system must first assert a valid address. the de vice is in the asynchronous mode when bit 15 of the c onfiguration register is set to '1'. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable ce# to valid data at the outputs. see 10.9.2, ac characteristics? asynchronous read on page 52 . 7.1.1 s29vs-r adm access with ce# low, we# high, and oe# high, the system pr esents the address to the device and sets avd# low. avd# is kept low for at least t avdp ns. the address is latched on the rising edge of avd#. 7.1.2 s29xs-r aadm access with ce# low, we# high, and oe# high, the system presents the upper address bits to dq and sets avd# low. the system then sets oe # low. the upper address bits are set when avd# goes high. the system then sets avd# low again, with oe# high to ca pture the lower address bi ts. the lower address bits are latched on the next rising edge of avd#. 7.2 synchronous (burst) read mo de and configuration register the device is capable of continuous sequential burst operation and linear bu rst operation of a preset length. in order to use synchronous (burst) read mode the co nfiguration register bit 15 must be set to 0. prior to entering burst mode, the system should determi ne how many wait states are needed for the initial word of each burst access (see table below), what mo de of burst operation is desired, how the rdy signal transitions with valid data, and output drive strength. the system would th en write the configuration register command sequence. see configuration register on page 29 for further details. when the appropriate number of wait states have occurred, data is output after the rising edge of the clk. subsequent words are output t bacc after the rising edge of each successi ve clock cycle, wh ich automatically increments the internal address counter. rdy in dicates the initial latency and any subsequent waits. 7.2.1 s29vs-r adm access to burst read data from the memory array in adm mode, the system must assert ce# to v il , and provide a valid address while driving avd# to v il for one cycle. oe# must remain at v ih during the one cycle that avd# is low. the data appears on a/dq15 -a/dq0 when ce # remains low, after oe# is low and the synchronous access times are satisfied. the next data in the burst sequence is read on each clock cycle that oe# and ce# remain low. oe# does not terminate a burs t access if it rises to v ih during a burst access. the outputs will go to high impedance but the burst access will contin ue until terminated by ce# going to v ih , or avd# returns to v il with a new address to initiate a another burst access. 7.2.2 s29xs-r aadm access to burst read data from the memory array in aadm mode, the system must assert ce# to v il , oe# must go low with avd# for one cycle while the upper address is valid. the rising edge of clk when oe# and avd# are low captures the upper 16 bits of address. th e rising edge of clk when oe# is high and avd# is low latches the lower 16 bits of address. the data app ears on a/dq15 -a/dq0 when ce# remains low, after oe# is low and the synchronous access times are satisfi ed. the next data in the burst sequence is read on each clock cycle that oe# and ce# remain low. once oe# returns to v ih during a burst read the oe# no longer enabl es the outputs until after avd# is at v il with oe# at v ih - which signals that address-low has been captured for the next burst access. this is so that oe# at v il may be used in conjunction with avd# at v il to indicate address-high on the a/dq signals without enabling the a/dq outputs, t hus avoiding data output co ntention with address-high.
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 25 data sheet (advance information) the device has a fixed internal address boundary that o ccurs every 128 words. a boundary crossing of one or two additional wait states is required. the time the device is outputting data with th e starting burst address not divisible by eight, addition al waits might be required. the following tables show the latency for variable wait state operation (note that ws = wait state). table 7.1 wait state vs. frequency wait state frequency (maximum mhz) 327 440 554 666 780 895 9104 10 120 table 7.2 address latency for 10 -13 wait states word initial wait subsequent clock cycles after initial wait states 0 10 -13 wait states d0 d1 d2 d3 d4 d5 d6 d7 +2 ws d8 1 d1d2d3d4d5d6d71 ws+2 wsd8 2 d2d3d4d5d6d71 ws1 ws+2 wsd8 3 d3d4d5d6d71 ws1 ws1 ws+2 wsd8 4 d4 d5 d6 d7 1 ws 1 ws 1 ws 1 ws +2 w s d8 5 d5 d6 d7 1 ws 1 ws 1 ws 1 ws 1 ws +2 ws d8 6 d6 d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws +2 ws d8 7 d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws +2 ws d8 table 7.3 address latency for 9 wait states word initial wait subsequent clock cycles after initial wait states 0 9 wait states d0 d1 d2 d3 d4 d5 d6 d7 +1 ws d8 1 d1d2d3d4d5d6d71 ws+1 wsd8 2 d2d3d4d5d6d71 ws1 ws+1 wsd8 3 d3d4d5d6d71 ws1 ws1 ws+1 wsd8 4 d4 d5 d6 d7 1 ws 1 ws 1 ws 1 ws +1 ws d8 5 d5 d6 d7 1 ws 1 ws 1 ws 1 ws 1 ws +1 ws d8 6 d6 d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws +1 ws d8 7 d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws +1 ws d8
26 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) table 7.4 address latency for 8 wait states word initial wait subsequent clock cycles after initial wait states 0 8 wait states d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d71 wsd8 2 d2d3d4d5d6d71 ws1 wsd8 3 d3 d4 d5 d6 d7 1 ws 1 ws 1 ws d8 4 d4 d5 d6 d7 1 ws 1 ws 1 ws 1 ws d8 5 d5 d6 d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 6 d6 d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 7 d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 table 7.5 address latency for 7 wait states word initial wait subsequent clock cycles after initial wait states 0 7 wait states d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8d9 2 d2d3d4d5d6d71 wsd8d9 3 d3 d4 d5 d6 d7 1 ws 1 ws d8 d9 4 d4 d5 d6 d7 1 ws 1 ws 1 ws d8 d9 5 d5 d6 d7 1 ws 1 ws 1 ws 1 ws d8 d9 6 d6 d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 7 d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 table 7.6 address latency for 6 wait states word initial wait subsequent clock cycles after initial wait states 0 6 wait states d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8d9 2 d2d3d4d5d6d7d8d9d10 3 d3 d4 d5 d6 d7 1 ws d8 d9 d10 4 d4 d5 d6 d7 1 ws 1 ws d8 d9 d10 5 d5 d6 d7 1 ws 1 ws 1 ws d8 d9 d10 6 d6 d7 1 ws 1 ws 1 ws 1 ws d8 d9 d10 7 d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 table 7.7 address latency for 5 wait states word initial wait subsequent clock cycles after initial wait states 0 5 wait states d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2 d3 d4 d5d6d7 d8 d9 2 d2d3 d4 d5 d6d7d8 d9d10 3 d3d4 d5 d6 d7d8d9d10d11 4 d4 d5 d6 d7 1 ws d8 d9 d10 d11 5 d5 d6 d7 1 ws 1 ws d8 d9 d10 d11 6 d6 d7 1 ws 1 ws 1 ws d8 d9 d10 d11 7 d7 1 ws 1 ws 1 ws 1 ws d8 d9 d10 d11
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 27 data sheet (advance information) table 7.8 address latency for 4 wait states word initial wait subsequent clock cycles after initial wait states 0 4 wait states d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2 d3 d4d5d6 d7 d8 d9 2 d2d3 d4 d5d6d7 d8 d9d10 3 d3d4 d5 d6d7d8 d9d10d11 4 d4d5 d6 d7d8d9d10d11d12 5 d5 d6 d7 1 ws d8 d9 d10 d11 d12 6 d6 d7 1 ws 1 ws d8 d9 d10 d11 d12 7 d7 1 ws 1 ws 1 ws d8 d9 d10 d11 d12 table 7.9 address latency for 3 wait states word initial wait subsequent clock cycles after initial wait states 0 3 wait states d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2 d3d4d5d6d7d8d9 2 d2d3 d4d5d6d7d8d9d10 3 d3d4 d5d6d7 d8 d9d10d11 4 d4d5 d6d7d8 d9d10d11d12 5 d5d6 d7d8d9d10d11d12d13 6 d6 d7 1 ws d8 d9 d10 d11 d12 d13 7 d7 1 ws 1 ws d8 d9 d10 d11 d12 d13
28 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 7.2.3 continuous burst the device continues to output seque ntial burst data from the memory array, wrapping around to address 0000000h after it reaches the highest addressable memo ry location, until the system drives ce# high, reset# low, or avd# low in conj unction with a new address. see table 6.6, device bus operations on page 20 . if the host system crosses a bank boundary whil e reading in burst mode, a nd the subsequen t bank is not programming or erasing, an address boundary crossing latency might be re quired. if the host system crosses the bank boundary while the subsequent bank is programmi ng or erasing, continuous burst halts (rdy will be disabled and data will continue to be driven). 7.2.4 8-, 16-word linear burst with wrap around the remaining two modes are fixed length linear burst with wrap around, in which a fixed number of words are read from consecutive addresses. in each of these modes, the burst a ddresses read are determined by the group within which the starting addre ss falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see table 7.10 ). as an example: if the starting addr ess in the 8-word mode is system byte address 3ch, the address range to be read would be byte address 30-3fh, and the burs t sequence would be 3c-3e-30-32-34-36-38-3ah. the burst sequence begins with the starting address written to the device, wraps back to the first address in the selected group, and outputs a maximum of 8 words. no additional wait states will be required within the 8- word burst. the 8th word will continue to be driven until the burst operation is aborted (ce# goes to v ih , a new address is latched in for a new burst operation, or a hardware reset). in a similar fashion, the 16-word linear wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. ad ditional wait states could be added the first time the device crosses from one to the other group of 8 word s in a 16-word burst. the number will depend on the starting address and the wait state set within the configuration register. see table 7.3 on page 21 to table 7.9 on page 27 . note that in these two burst read mode s the address pointer does not cross the boundary that occurs every 128 words; thus, no ad dress boundary crossing wait states are inserted for linear burst with wrap. table 7.10 burst address groups mode group size group byte address ranges 8-word 16 bytes 0-fh, 10-1fh, 20-2fh,... 16-word 32 bytes 0-1fh, 20-3fh, 30-4fh,...
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 29 data sheet (advance information) figure 7.1 synchronous read note 1. required only if device is performing a continuous burst operation. 7.2.5 configuration register configuration register (cr) sets various operatio nal parameters associated wit h burst mode. upon power-up or hardware reset, the device defaults to the idle state, and the configuration register settings are in their default state. the host system should determine the proper settin gs for the configuration register, and then execute the set configuration register command se quence, before attempting burst operations. the configuration register can also be read using a command sequence (see table 11.1 on page 60 ). the table below describes the register settings and indicates the default state of each bit after power-on or a hardware reset. the configuration register bits are not affected by a command reset. load initial address address = ra read initial data rd = dq[15:0] read next data rd = dq[15:0] wait programmable wait state setting wait x clocks (if required): additional latency due to starting address and clock frequency end of data? yes crossing boundary? (note 1) no yes completed ra = read address rd = read data cr0.14 - cr0.11 sets initial access time (from address latched to valid data) from 3 to 13 clock cycles no
30 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 7.2.5.1 device read mode configuration register bit 15 (cr.15) controls w hether read accesses via the bus interface are in asynchronous or burst mode. asynchronous mode is t he default after power-on or hardware reset. write accesses are always conducted with asynchronous mode timing, independent of the read mode. 7.2.5.2 wait states configuration register bits 14 to 11 (cr.[14..11]) define the number of delay cycles after the avd# low cycle that captures the initial ad dress until the cycle that read data is valid. the bits from 14 to 11 are in most to least significant order. the random address access at the beginning of each read burst takes longer than the subsequent read cycles . the memory bus interface mu st be told how many cycles to wait before driving valid data then advancing to the next data wo rd. the number of initial wait cycles will vary with the memory clock rate. the number of wait states is found in the wait state table information abo ve. the minimum number of wait cycles is three. the maximu m is 13. the default after power-o n or hardware reset is 13 cycles. when the appropriate number of wait st ates have occurred, data is output after the rising edge of the clk. subsequent words are output t bacc after the rising edge of each successi ve clock cycle, wh ich automatically increments the internal address counter. 7.2.5.3 rdy polarity configuration register bit 10 (cr.10) controls whet her the rdy signal indicates valid data when high or when low. when this bit is zero the rdy signal indicates data is valid when the signal is low. when this bit is one the rdy signal indicates data is valid when the signal is high. the default for this bit is set to one after power-on or a hardware reset. table 7.11 configuration register cr bit function settings (binary) cr.15 device read mode 0 = synchronous read mode 1 = asynchronous read mode (default) cr.14 cr.13 cr.12 cr.11 programmable read wait states 0000 = initial data is valid on the reserved rising clk edge after addresses are latched 0001 = 3rd 0010 = 4th 0011 = 5th . . . . . . 1011 = 13th (default) 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved cr.10 rdy polarity 0 = rdy signal is active low 1 = rdy signal is active high (default) cr.9 reserved 0 = reserved 1 = reserved (default) cr.8 rdy timing 0 = rdy active one clock cycle before data 1 = rdy active with data (default) cr.7 output drive strength 0 = full drive= current driver strength (default) 1 = half drive cr.6 reserved 0 = reserved 1 = reserved (default) cr.5 reserved 0 = reserved (default) 1 = reserved cr.4 reserved 0 = reserved (default) 1 = reserved cr.3 reserved 0 = reserved 1 = reserved (default) cr.2 cr.1 cr.0 burst length 000 = continuous (default) 010 = 8-word (16-byte) linear burst with wrap around 011 = 16-word (32-byte) linear burst with wrap around (all other bit settings are reserved)
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 31 data sheet (advance information) 7.2.5.4 rdy timing configuration register bit 8 (cr.8) controls whether the rdy signal indicates valid data on the same cycle that data is valid or one cycle before data is valid. when this bit is zero the rdy signal indicates data is valid in the same cycle the data is valid. when this bit is one the rdy signal indicates data is valid one cycle before data is valid. the default for this bit is se t to one after power-on or a hardware reset. 7.2.5.5 output drive strength configuration register bit 7 (cr.7) co ntrols whether the data outputs drive with full or half strength. when this bit is zero the data outputs drive with full strength. when this bit is one the data outputs drive with half strength. the default for this bit is clear ed to zero after power-on or a hardware reset. 7.2.5.6 burst length configuration register bits 2 to 0 (cr.[2..0]) define the length of burst read accesses. the bits from 2 to 0 are in most to least significant order. see the register table for code meaning & default value. 7.3 status register the status of program and erase oper ations is provided by a status regi ster. a status register read command is written followed by a read of the status register for each access of the status register information. the clear status register command will reset t he status register. the status regi ster can be read in synchronous or asynchronous mode. notes: 1. status bits higher than bit 7 are undefined. 2. bit 7 reflects the device status. 3. if the device is busy, bit 0 is used to check whether the addressed bank is busy or some other bank is busy. 4. all the other bits reflect the status of the device. notes: 1. bit 7 is set when there is no erase or program operation in progress in the device. 2. bits 1 through 6 are valid if and only if bit 7 is set. table 7.12 status register reset state bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready bit. overall status erase suspend status bit erase status bit program status bit rfu program suspend status bit sector lock status bit bank status bit drb 1 at reset essb 0 at reset esb 0 at reset psb 0 at reset rfu 0 at reset pssb 0 at reset slsb 0 at reset bsb 0 at reset table 7.13 status register - bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready bit. overall status erase suspend status bit erase status bit program status bit rfu program suspend status bit sector lock status bit bank status bit drb essb esb psb rfu pssb slsb bsb 0 device busy programming or erasing invalid invalid invalid invalid invalid invalid valid 1 device ready valid valid valid valid valid valid valid
32 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) notes 1. upon issuing the ?erase suspend? command, the user must continue to read status until drb becomes 1 before accessing another sector within the same bank. 2. cleared by ?erase resume? command. notes 1. esb bit reflects ?success? or ?failure? of the most recent erase operation. 2. cleared by ?clear status register? command as well as by hardware reset. notes 1. psb bit reflects ?success? or ?failure? of the most recent program operation. 2. cleared by ?clear status register? command as well as by hardware reset. table 7.14 status register - bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready bit. overall status erase suspend status bit erase status bit program status bit rfu program suspend status bit sector lock status bit bank status bit drb essb esb psb rfu pssb slsb bsb 1 bits 6:1 only valid when bit 7 = 1 0 no erase in suspension xxxxxx 1 bit 6:1 only valid when bit 7 = 1 1 erase in suspension xxxxxx table 7.15 status register - bit 5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready bit. overall status erase suspend status bit erase status bit program status bit rfu program suspend status bit sector lock status bit bank status bit drb essb esb psb rfu pssb slsb bsb 1 bits 6:1 only valid when bit 7 = 1 x 0 erase successful xxxxx 1 bit 6:1 only valid when bit 7 = 1 x 1 erase error xxxxx table 7.16 status register - bit 4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready bit. overall status erase suspend status bit erase status bit program status bit rfu program suspend status bit sector lock status bit bank status bit drb essb esb psb rfu pssb slsb bsb 1 bits 6:1 only valid when bit 7 = 1 xx 0 program successful xxxx 1 bit 6:1 only valid when bit 7 = 1 xx 1 program fail xxxx
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 33 data sheet (advance information) notes 1. this register is reserved for future use. 2. cleared by ?clear status register? command as well as by hardware reset. notes 1. upon issuing the ?program suspend? command, the user must continue to read status until drb becomes 1 before accessing anothe r sector within the same bank. 2. cleared by ?program resume? command. notes 1. slsb indicates that a program or erase operation failed to program or erase because the sector was locked or the operation wa s attempted on the protect ed secure silicon region. 2. slsb reflects the status of the most recent program or erase operation. 3. slsb is cleared by ?clear status register? or by hardware reset. table 7.17 status register - bit 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready bit. overall status erase suspend status bit erase status bit program status bit rfu program suspend status bit sector lock status bit bank status bit drb essb esb psb rfu pssb slsb bsb 1 bits 6:1 only valid when bit 7 = 1 xxx xxxx table 7.18 status register - bit 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready bit. overall status erase suspend status bit erase status bit program status bit rfu program suspend status bit sector lock status bit bank status bit drb essb esb psb rfu pssb slsb bsb 1 bits 6:1 only valid when bit 7 = 1 xxxx 0 no program in suspension xx 1 bit 6:1 only valid when bit 7 = 1 xxxx 1 program in suspension xx table 7.19 status register - bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready bit. overall status erase suspend status bit erase status bit program status bit rfu program suspend status bit sector lock status bit bank status bit drb essb esb psb rfu pssb slsb bsb 1 bits 6:1 only valid when bit 7 = 1 xxxxx 0 sector not locked during operation x 1 bit 6:1 only valid when bit 7 = 1 xxxxx 1 sector locked error x
34 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) notes 1. bsb is used to check if a program or er ase operation in progress in the current bank. 7.4 blank check the blank check command will confirm if the selected sector is erased. the blank check command does not allow for reads to th e array during the blank check. reads to the array while this command is executing will return unknown data. ? to initiate a blank check on sector x, write 33h to addr ess 555h in sector x. while the device is in the idle state (not during program suspend, not during erase suspend, ...). ? the blank check command may not be written while the device is actively programming or erasing. blank check does not support simultaneous operations. ? use the status register read to confirm if the device is still busy an d when compete if the sector is blank or not. ? bit 5 of the status register will be cleared to zero if the sector is erased and set to one if not erased. ? bit 7 & bit 0 of the status register will show if the de vice is performing a blank check (similar to an erase operation). ? as soon as any bit is found to not be erased, the device will halt the operation and report the results. ? once the blank check is completed, the device will to return to the idle state. 7.5 simultaneous read/write the simultaneous read/write f eature allows the host system to read da ta from one bank of memory while programming or erasing another bank of memory. an er ase operation may also be suspended to read from or program another location within the same bank (note: programming to the sector being erased is not allowed). figure 10.14, back-to-back read/write cycle timings on page 58 shows how read and write cycles may be initiated for simultaneous ope ration with zero latency. refer to the dc characteristics on page 48 table for read-while-program and re ad-while-erase current specification. table 7.20 status register - bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready bit. overall status erase suspend status bit erase status bit program status bit rfu program suspend status bit sector lock status bit bank status bit drb essb esb psb rfu pssb slsb bsb 0 bits 6:1 only valid when bit 7 = 1 xxxxxx 0 program or erase op. in addressed bank 0 bits 6:1 only valid when bit 7 = 1 xxxxxx 1 program or erase op. in other bank 1 bit 6:1 only valid when bit 7 = 1 xxxxxx 0 no active program or erase op. 1 bit 6:1 only valid when bit 7 = 1 xxxxxx 1 invalid
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 35 data sheet (advance information) 7.6 writing commands/command sequences the device accepts asynchronous write bus operations. during an asynchronous write bus operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address and data. when latching an address, avd# must be driven to v il . addresses are latched on the first falling edge of we# or on the rising edge of avd#, while data is latched on the 1st rising edge of we#. see the table 6.6, device bus operations on page 20 for the signal combinations that define each phase of a write bus operation to the device. each write is a command or part of a command sequence to the device. the address provided in each write operation may be a bit pattern used to help identify the write as a command to the device. the upper portion of the address may also select the bank or sector the command operation is to be performed. a bank address (ba) is the set of address bits required to uniquely select a bank. similarly, a sector address (sa) is the address bits required to uniquely select a sector. the data in each wr ite identifies the command operation to be performed or supplies informati on needed to perform the operation. see table 11.1, command definitions on page 60 for a listing of the commands accepted by the device. i cc2 in dc characteristics on page 48 represents the active current specif ication for a write (embedded algorithm) operation. 7.7 program/erase operations for any program and/or erase operations, including writing command sequences, the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or programming data. addresses are latched on the first falling edge of we# or rising edge of avd# during asynchronous writes. data is latched on the rising edge of we# during asynchronous writes. note the following: ? when the embedded program algorithm is complete, the device returns to the calling routing (erase suspend, ssr lock, secure silicon region, or idle state). ? the system can determine the status of the program operation by reading the status register. refer to status register on page 31 for information on these status bits. ? a 0 cannot be programmed back to a 1 . a succeeding read shows that the data is still 0. only erase operations can convert a 0 to a 1 . ? any commands written to the device during the embedded program algorithm are ignored except the reads from the non-programming bank, program su spend, and status read command. any commands written to the device during the embedded erase algorithm are ignored except reads from the non- erasing bank, erase suspend and status read command. ? a hardware reset immediately terminates the program/erase operation and the program command sequence should be reinitiated once the device has returned to the idle state, to ensure data integrity. old data 0011 new data 0101 results 0001
36 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 7.7.1 write buffer programming write buffer programming allows the system to write 1 to 64 bytes in one programming operation. the write buffer programming command sequence is initiated by fi rst writing the write buffer load command written at the sector address + 555h in wh ich programming occurs. next, th e system writes the number of word locations minus 1 at the sector address + 2aah. this tells t he device how many write buffer addresses are loaded with data and therefore when to expect the program buffer to flash confirm command. the sector address must match during the writ e buffer load command and during the write word count command and the sector must be unlocked or the operation will abort and return to the initiating state. the write buffer is used to program data within a 64 byte page aligned on a 64 byte boundary. thus, a full page write buffer programming operation must be alig ned on a page boundary. programming operations of less than a full page may start on any word boundary but may not cross a page boundary. the system then writes the starting address/data combination. this starti ng address is the first address/data pair to be programmed, and selects the write-buffer-page address. the sector addr ess must match the write buffer load sector address or the operation will abort and return to the initiating state. all subsequent address/data pairs must be in sequential order. all writ e buffer addresses must be within the same page. if the system attempts to load data outside this range, the operation aborts after the write to buffer command is executed and the device will indicate a program fail in the status register at bit locati on 4 (psb). a ?clear status register? must be issued to clear the psb status bit. the counter decrements for each data load operation. once the specified number of writ e buffer locations have been load ed, the system must then write the program buffer to flash command at the sector addre ss + 555h. the device then goes busy . the embedded program algorithm automatica lly programs and verifies the data for the correct data pattern. the system is not required to provide any controls or timings during t hese operations. if the incorre ct number of write buffer locations have been loaded and the program buffer to flash command is issued, the status register will indicate a program fail at bit location 4 (psb). a ?cl ear status register? must be issued to clear the psb status bit. the write-buffer embedded programming operation can be suspended using the program suspend command. when the embedded program algorithm is comp lete, the device then returns to erase suspend, ssr lock, secure silicon region, or idle state. th e system can determine th e status of the program operation by reading the status register. refer to status register on page 31 for information on these status bits. the write buffer programming sequence can be aborted in the following ways: ? load a value greater than the buffer size during the number of locations step. ? write an address that is outside the p age of the starting address during t he write buffer data loading stage of the operation. the write buffer programming seque nce can be stopped and reset by the following: hardware reset or power cycle.
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 37 data sheet (advance information) software functions and sample code notes: 1. base = base address. 2. last = last cycle of write buffer program operation; depend ing on number of words written, the total number of cycles may be from 6 to 37. 3. for maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (n words) possible . the following is a c source code example of using the write buffer program function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: write buffer programming command */ /* notes: write buffer programming limited to 32 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *( (uint16 *)sector_address + 0x555 ) = 0x0025; /* write write buffer load command */ *( (uint16 *)sector_address + 0x2aa) = wc; /* write word count (minus 1) */ do{ *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ wc--; /* decrement word count */ }while ( wc >= 0 ); /* do it again */ *( (uint16 *)sector_address + 0x555) = 0x0029; /* write confirm command */ /* poll for completion */ table 7.21 write buffer program cycle description operation byte address word address data 1 write buffer load command write sector address + aaah sector address + 555h 0025h 2 write word count write sector address + 555h sector address + 2aa word count (n?1)h number of words (n) loaded into the write buffer can be from 1 to 32 words. 3 to 34 load buffer word n write program address, word n word n last write buffer to flash write sector address + aaah sector address + 555h 0029h
38 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 7.7.2 program suspend/p rogram resume commands the program suspend command allows the system to interrupt an embedded programming operation or a write to buffer programming operation so that data can read from any non-suspended sector. when the program suspend command is written during a progra mming process, the device halts the programming operation within t psl (program suspend latency) and updat es the status bits. addresses are don't-cares when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non- suspended sector and page. the program suspend co mmand may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. after the program resume command is written, the devi ce reverts to programming and the status bits are updated. the system can determine the st atus of the program operation by reading the status register, just as in the standard program operation. see status register on page 31 for more information. the system must write the program resume command to exit the program sus pend mode and continue the programming operation. further writ es of the program resume comma nd are ignored. another program suspend command can be written after the device has resumed programming. software functions and sample code the following is a c source code example of usin g the program suspend function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for gen eral information on spansion flash memory software development guidelines. /* example: program suspend command */ *( (uint16 *)bank_addr + 0x000 ) = 0x0051; /* write suspend command */ the following is a c source code example of usi ng the program resume function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for gen eral information on spansion flash memory software development guidelines. /* example: program resume command */ *( (uint16 *)sector_address + 0x000 ) = 0x0050; /* write resume command */ table 7.22 program suspend cycle operation byte address word address data 1 write bank address bank address 0051h table 7.23 program resume cycle operation byte address word address data 1 write sector address + 000h sector address + 000h 0050h
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 39 data sheet (advance information) 7.7.3 sector erase the sector erase function erases one sector in the memory array. (see table 11.1 on page 60 ) the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. after a successful sector erase, al l locations within the erased sector c ontain ffffh. the system is not required to provide any controls or timings dur ing these operations. sector erase r equires 2 commands. each of the sector addresses must match, the lower addresses must be correct, and the sector must be unlocked previously by executing the sector unlock command and must not be locked by the sector lock range command. when the embedded erase algorithm is complete, the bank returns to idle state and addresses are no longer latched. note that while the embedded erase operatio n is in progress, the syst em can read data from the non-erasing banks. the system can determine the st atus of the erase operation by reading the status register. see status register on page 31 for information on these status bits. once the sector erase operation ha s begun, only reading from outside the erase bank, read of status register, and the erase suspend command are valid. al l other commands are ignored . however, note that a hardware reset immediately terminates the erase operat ion. if that occurs, the sector erase command sequence must be reinitiated once the device has re turned to idle state, to ensure data integrity. see program/erase operations on page 35 for parameters and timing diagrams. software functions and sample code the following is a c source code example of us ing the sector erase function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: sector erase command */ *( (uint16 *)sector_address + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)sector_address + 0x2aa) = 0x0030; /* write sector erase command */ 7.7.4 chip erase the chip erase function erases the complete memory array. (see table 11.1 on page 60 ). the device does not require the system to preprogram prior to eras e. the embedded eras e algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. after a successful chip erase, all locations within the device contain ffffh. the system is not re quired to provide any controls or timings during these operations. chip erase requires 2 commands. each of the sector addresses must match, the lower addresses must be correct, and sect or 0 must be unlocked previously by executing the sector unlock command. if any sector has been locked by the sector lock range command, the chip erase command will not start. when the embedded erase algorithm is complete, the dev ice returns to idle state and addresses are no longer latched. note that while the embedded erase o peration is in progress, the system can not read data from the device. the system can determi ne the status of the erase operatio n by reading the status register. see status register on page 31 for information on these status bits. once the chip erase operat ion has begun, onl y a status read, hardware reset or power cycle are valid. all other commands are ignored. however, note that a ha rdware reset or power cycle immediately terminates the erase operation. if th at occurs, the chip erase command sequence must be reinitiated once the device has returned to idle state, to ensure data integrity. see program/erase operations on page 35 for parameters and timing diagrams. table 7.24 sector erase cycle description operation byte address word address data 1 setup command write sector address + aaah sector address + 555h 0080h 2 sector erase command write sector address + 555h sector address + 2aa 0030h
40 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) software functions and sample code the following is a c source code example of us ing the chip erase function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: chip erase command */ /* note: cannot be suspended */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x2aa ) = 0x0010; /* write chip erase command */ 7.7.5 erase suspend/erase resume commands the erase suspend command allows the system to inte rrupt a sector erase operation and then read data from, or program data to, the device. this command is valid only during the sector erase operation. the erase suspend command is ignored if wr itten during the chip erase operation. when the erase suspend command is written during the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase operation and update the status bits. after the erase operation has been suspended, the ba nk enters the erase-suspend mode. the system can read data from or program data to the device. r eading at any address within erase-suspended sectors produces undetermined data. the system can read the status regi ster to determine if a sector is actively erasing or is erase-suspended. refer to status register on page 31 for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend mode. the system can determine the status of the program operatio n by reading the status register, just as in the standard program operation. to resume the sector erase operat ion, the system must write the er ase resume command. the device will revert to erasing and the status bi ts will be updated. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. table 7.25 chip erase cycle description operation byte address word address data 1 setup command write base + aaah base + 555h 0080h 2 chip erase command write base + 555h base + 2aa 0010h
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 41 data sheet (advance information) software functions and sample code the following is a c source code example of us ing the erase suspend function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for gen eral information on spansion flash memory software development guidelines. /* example: erase suspend command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of us ing the erase resume function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for gen eral information on spansion flash memory software development guidelines. /* example: erase resume command */ *( (uint16 *)sector_address + 0x000 ) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ 7.7.6 accelerated program/sector erase accelerated write buffer programming, and sect or erase operations are enabled through the v pp function. this method is faster than the standard chip program and sector erase command sequences. the accelerated write buffer program and sector er ase functions must not be used more than 50 times per sector. in addition, accelerated write buffer progra m and sector erase should be performed at room temperature (30 c 10 c). if the system asserts v hh on v pp , the device automatically uses the higher voltage on the input to reduce the time required for program and erase operations. removing v hh from the v pp input, upon completion of the embedded program or erase operation, returns the device to normal operation. ? simultaneous operations are not supported while v pp is at v hh . the v pp pin must not be at v hh for operations other than accelerated write buffer programmi ng, accelerated sector eras e, and status register read or device damage may result. ? the v pp pin must not be left floating or unconnected; inconsistent behavior of the device may result. ? there is a minimum of 100 ms required between accele rated write buffer programming and a subsequent accelerated sector erase. table 7.26 erase suspend cycle operation byte address word address data 1 write bank address bank address 00b0h table 7.27 erase resume cycle operation byte address word address data 1 write sector address + 000h sector address + 000h 0030h
42 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 7.8 handshaking the handshaking fe ature allows the host system to det ect when data is ready to be read by simply monitoring the rdy (ready) pin, which is a dedi cated output controlled by ce#. when ce# input is low, the rdy output signal is active ly driven. when both of the ce# inputs are high the rdy output is high-impedance. when ce# input and oe# input is low, t he a/dq15-a/dq0 output signals are actively driven. when both of the ce# inputs are hig h, or the oe# input is hi gh, the a/dq15- a/dq0 outputs are high-impedance. when the device is operated in synchronous mode, and oe # is low (active), the initial word of burst data becomes available after the rising edge of the rdy. cr.8 in the configuration register allows the host to specify whether rdy is active at t he same time that data is ready, or one cycle be fore data is ready (see table 7.11 on page 30 ). when the device is operated in asynchronous mode , rdy will be high when ce# is low (active). 7.9 hardware reset the reset# input provides a hardware method of resett ing the device to idle state. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, resets the configuration re gister, and ignores all read/write commands for the duration of the reset operation. the device also resets the internal state machine to idle state. hardware reset clears the aadm upper address register to zero. to ensure data integrity the operation that was interrupted should be rein itiated once the device is ready to accept another command sequence. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. see figure 10.10 for timing diagrams 7.10 software reset software reset is part of the command set (see table 11.1 on page 60 ) that also returns the device to idle state and must be used for the following conditions: 1. exit id/cfi mode 2. exit secure silicon region mode 3. exit configuration register mode 4. exit ssr lock mode reset commands are ignored once programming/erasure has begun until the operation is complete. software functions and sample code note: base = base address. the following is a c source code example of using the reset function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; table 7.28 reset cycle operation byte address word address data reset command write base + xxxh base + xxxh 00f0h
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 43 data sheet (advance information) 8. sector protection/unprotection the sector protection/unprotection f eature disables or enables programmi ng or erase operations in one or multiple sectors and can be implemented through soft ware and/or hardware methods, which are independent of each other. this section describes the various method s of protecting data stored in the memory array. 8.1 sector lock/unlock command the sector lock/unlock command sequence allows the syst em to protect all sectors from accidental writes or, unprotect one sector to allow programming or eras ing of the sector. when the device is first powered up, all sectors are unlocked. to lock al l sectors (enter protec ted mode), a sector lock/unlock command must be issued to any sector address. once this command is i ssued, only one sector at a time can be unlocked until power is cycled. to unlock a sector, the system must write the sector lock/unlock command sequence. two cycles are first written: addresses are x555h and x2aah, and data is 60h. during the third cycle, the sector address (sla) and unlock command (60h) are written, while specifying with address a6 whether that sector should be locked (a6 = v il ) or unlocked (a6 = v ih ). a program or erase operation will check the unlocked sector address only at the beginning of the program or erase operation. it is not necessary to keep the sector being programmed or erased unlocked during the operation. the system can change the unlocked sector a fter programming or erasing the sector has begun. an erase resume or program resume command does not check the value of the unlocked sector. if a6 is set to v il ,then all sectors in the array will be locked. only one sector at a time can be unlocked. if a sector lock/unlock command is i ssued to a sector that is protect ed by the sector lock range command, all sectors in the part will be locked. 8.2 sector lock range command this command allows a range of sectors to be protect ed from program or erase (locked) until a hardware reset or power is removed from the device. this command causes the sector lock/unlock command to be ignored for the range of sectors. two cycles are firs t written: addresses are x555h and x2aah, and data is 60h. during the third cycle, t he sector address (sla) and load sector a ddress command (61h) is written. this cycle sets the lower sector address of the range. during the f ourth cycle, the sector address (sla) and load sector address command (61h) is written. this cycl e sets the upper sector address of the range. the addresses reference a large sector address range (128 kb ). if a sector address ma tches the location of the four small sectors, all of the small sectors will be protected as a group. the sectors selected by the lower and upper address, as well as all sectors between these se ctors, are protected from program and erase until a hardware reset or power is removed. if the lower and upper sector addresses are for the same sector then only that one sector is locked. fl ash address input a6 (system byte address bit a7) during both address cycles must be zero (a6 = v il ) for the addresses to be accepted as valid. if the first sector address cycle contains an address which is higher than the second sector address cycle, then the command sequence will be invalid. if a6 is set to one (a6 = v ih ) on either address cycle, the command sequence will disable subsequent sector lock range commands. a valid sector lock range command sequence is accepted only once after a hardware reset or initial power up. additional sector lock range commands will be ignored. if a sector unlock command tries to unlock a sector with in the sector lock range, the sector will remain in locked state. similarly, if a sector that is currently unlocked by the sector unlock command is overlapped by a subsequent sector lock range, that sector will be lo cked and program erase operations to that region will be ignored. this command is generally used by tr usted boot code. after power on reset boot code has the option to check for any need to update sectors before locking them for the remainder of power on time. once boot code is satisfied with the content of sectors to be protected the sector lock range command is used to lock sectors against any program or eras e during normal system operat ion. this adds an extra layer of protection for critical data that must be protected against accidental or malicious corruption. yet, main tains flexibility for trusted boot code to perform occasional updates of the dat a. it is important to issue the sector lock range command even if no sectors are to be protected so that sectors that should remain available for update cannot be later locked by accidental or malicious code behavior.
44 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 8.3 hardware data protection methods there are additional hardware methods by which intended or accidental erasure of any sectors can be prevented via hardware means. the followin g subsections describes these methods: 8.3.1 v pp method once v pp input is set to v il , all program and erase functions are disa bled and hence all sectors (including the secure silicon region) are protected. 8.3.2 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper sig nals to the control inputs to prevent unintentional writes when v cc is greater than v lko . 8.3.3 write pulse glitch protection noise pulses of less than 3 ns (typical) on oe#, we#, or ce# do not initiate a write cycle. 8.3.4 power-up write inhibit if ce# = reset# = v il and oe# = v ih during power up, the device does not accept write commands. the internal state machine is automatically reset to the idle state on power-up. 8.4 ssr lock the ssr lock consists of two bits. the customer secure silicon region protection bit is bit 0. the factory secure silicon region protection bit is bit 1. all other bits in this register return ?1.? if the customer secure silicon region protection bit is set to ?0,? the customer secure silicon region is protected and can not be programmed. if this bit is set to ?1,? the customer secure silicon region is available for programming. once this area has been programmed, the ssr lock bit 0 should be programmed to ?0.? 8.5 secure silicon region the secure silicon region provides an extra fl ash memory region that may be programmed once and permanently protected from fu rther programming or erase. ? reads can be performed in the asynchronous or synchronous mode. ? sector address supplied during the secure silicon en try command selects the flash memory array sector that is overlaid by the secure silicon region address map. ? continuous burst mode reads within secure silicon region wrap from address ffh back to address 00h. ? reads outside of the overlaid sector return memory array data. ? the secure silicon region is not accessible when the device is executing an embedded algorithm (nor during program suspend, erase suspend, or while another aos is active). ? see the secure silicon address map for address range of this area. 8.5.1 factory secur e silicon region the factory secure silicon region is always protec ted when shipped from the factory and has the factory ssr lock bit (bit 1) permanently set to a zero. this prevents cloning of a factory locked part and ensures the security of the esn and customer code once the product is shipped to the field.
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 45 data sheet (advance information) 8.5.2 customer s ecure silicon region the customer secure silicon region is typically shipped unprotected, customer ssr lock bit (bit 0) set to a one, allowing customers to utilize that sector in any manner they choose. ? the customer secure silicon region can be read any number of times, but each word cl can be programmed only once and the region locked only once. the customer secure silicon region lock must be used with caution as once locked, there is no pr ocedure available for unlocking the customer secure silicon region area and none of the bits in the cu stomer secure silicon region memory space can be modified in any way. the customer indicator bit is located in the ssr lock at bit location 0. ? once the customer secure silicon region area is prot ected, any further attempts to program in the area will fail with status indicating the area being programmed is protected. 8.5.3 secure silicon region entry and exit command sequences the system can access the secure silicon region regi on by issuing the one-cycle enter secure silicon region entry command sequence from t he idle state. the device continues to have access to the secure silicon region region until the system issues the exit secure silicon region command sequence, performs a hardware reset, or until power is removed from the device. see command definition table [secure silicon region command table, appendix table 11.1 on page 60 for address and data requirements for both command sequences. the secure silicon region entry command allows the following commands to be executed ? read customer and factory secure silicon regions ? program the customer secure silicon region ? read data out of all sectors not re-mapped to secure silicon region ? secure silicon region exit software functions and sample code the following are c functions and source code examples of using the secured silicon sector entry, program, and exit commands. refer to the spansion low level driver user?s guide (available soon on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: secsi sector entry command */ *( (uint16 *)sector_address + 0x555 ) = 0x0088; /* write secsi sector entry cmd */ /* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ table 8.1 secured silicon region entry cycle operation byte address word address data entry cycle write sector address + aaah sector address + 555h 0088h table 8.2 secured silicon region program cycle operation byte address word address data program setup write sector address + aaah sector address + 555h 0025h write word count write sector address + 555h sector address + 2aa word count (n?1)h number of words (n) loaded into the write buffer can be from 1 to 32 words. load buffer word n write program address, word n word n write buffer to flash write sector address + aaah sector address + 555h 0029h
46 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) /* example: secsi sector exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* write secsi sector exit cycle */ 9. power conservation modes 9.1 standby mode in the standby mode current consumption is greatly reduc ed, and the outputs (a/dq 15-a/dq0) are placed in the high impedance state, independent of the oe# in put. the device enters the cmos standby mode when the ce# and reset # inputs are bo th held at v cc 0.2 v. the device requires standard access time (t ce or t ia ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in dc characteristics on page 48 represents the standby current specification 9.2 automatic sleep mode the automatic sleep mode minimizes flash device e nergy consumption while in asynchronous mode and while the device is not in a suspended state. the device aut omatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is inde pendent of the ce#, we #, and oe# control signals. standard address access timings (t acc or t pac c ) provide new data when addresses are changed. while in sleep mode, output data is latched and alwa ys available to the system. while in synchronous mode, the automatic sleep mode is disabled. i cc6 in dc characteristics on page 48 represents the automatic sleep mode current specification. 9.3 output disable (oe#) when the oe# input is at v ih , output (a/dq15-a/dq0) from the device is disabled and placed in the high impedance state. rdy is not controlled by oe#. table 8.3 secured silicon region exit cycle operation byte address word address data exit cycle write base ad dress base address 00f0h
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 47 data sheet (advance information) 10. electrical specifications 10.1 absolute maximum ratings notes 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 10.2 . 2. minimum dc input voltage on pin v pp is -0.5v. during voltage transitions, v pp may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10.1 . maximum dc voltage on pin v pp is +9.5 v, which may overshoot to 10.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 10.1 maximum negative overshoot waveform figure 10.2 maximum positive overshoot waveform 10.2 operating ranges note: operating ranges define those limits between wh ich the functionality of the device is guaranteed. storage temperature plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground: all inputs and i/os except as noted below (note 1) ?0.5 v to vio + 0.5 v v cc (note 1) ?0.5 v to +2.5 v v io ?0.5 v to +2.5 v v pp (note 2) ?0.5 v to +9.5 v output short circuit current (note 3) 100 ma 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v wireless (i) devices ambient temperature (t a ) ?25c to +85c ambient temperature (limited set of conditions for embedded devices) ?40c to +85c supply voltages v cc supply voltages +1.70 v to +1.95 v v io supply voltages +1.70 v to +1.95 v v cc(min) >= v io(min) - 200mv
48 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 10.3 dc characteristics 10.3.1 cmos compatible notes 1. maximum i cc specifications are tested with v cc = v cc max. 2. v cc = v io 3. i cc active while embedded erase or embedded program is in progress. 4. device enters automatic sleep mode when addresses are stable for t acc + 20 ns. typical sleep mode current is equal to i cc3 . 5. total current during accelerated programming is the sum of v pp and v cc currents. 6. i cc5 applies while reading the status register during program and erase operations. 7. effect of status register polling during write not included. parameter description test conditions (notes 1 & 2 ) min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v il , we# = v ih , burst length = 8 66 mhz 30 33 ma 83 mhz 32 36 ma 104 mhz 36 44 ma ce# = v il , oe# = v il , we# = v ih , burst length = 16 66 mhz 30 35 ma 83 mhz 32 38 ma 104 mhz 36 40 ma ce# = v il , oe# = v il , we# = v ih , burst length = continuous 66 mhz 32 39 ma 83 mhz 36 42 ma 104 mhz 40 44 ma i io1 v io non-active output oe# = v ih , rdy = tri-state 20 30 a i io2 v io standby ce# = reset# = v cc 0.2v 2 3 a i cc1 v cc active asynchronous read current ce# = v il , oe# = v il , we# = v ih 10 mhz 40 80 ma 5 mhz 20 40 ma 1 mhz 10 20 ma i cc2 v cc active write current (3) (7) ce# = v il , oe# = v ih , v pp = v ih v pp 15a v cc 30 40 ma i cc3 v cc standby current ce# = reset# = v cc 0.2 v v pp 15a v cc 30 40 a i cc4 v cc reset current reset# = v il, clk = v il 150 250 a i cc5 v cc active current (read while write) (6) ce# = v il , oe# = v il , v pp = v ih continuous burst 66 mhz 64 78 ma 83 mhz 68 104 mhz 72 i cc6 v cc sleep current (4) ce# = v il , oe# = v ih 20 40 a i pp accelerated program current (5) ce# = v il , oe# = v ih, v pp = 9.5 v v pp 710ma v cc 25 28 ma v il input low voltage v io = 1.8 v ?0.2 0.4 v v ih input high voltage v io = 1.8 v v io ? 0.4 v io + 0.4 v ol output low voltage i ol = 100 a, v cc = v cc min = v io 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min = v io v io ? 0.1 v v hh voltage for accelerated program 8.5 9.5 v v lko low v cc lock-out voltage 1.0 1.1 v
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 49 data sheet (advance information) 10.4 capacitance notes 1. test conditions t a = 25c, f = 1.0 mhz 2. sampled, not 100% tested. 10.5 ac test conditions figure 10.3 input pulse and test point figure 10.4 output load symbol description test condition min. typ. max. unit c in input capacitance (address, ce#, oe#, we#, avd#, we#, clk, reset#) v in = 0 single die 2.0 4.5 6.0 pf dual die 4.0 9.0 12.0 pf c out output capacitance (dq, rdy) v out = 0 single die 2.0 4.5 6.0 pf dual die 4.0 9.0 12.0 pf operating range input level 0.0 to v io input comparison level v io /2 output data comparison level v io /2 load capacitance (c l ) 30 pf transition time (t t ) (input rise and fall times) 66 mhz 3.00 ns 83 mhz 2.50 ns 104 mhz 1.85 ns transition time (t t ) (clk input rise and fall times) 66 mhz 3.00 ns 83 mhz 2.50 ns 104 mhz 1.85 ns v io v io /2 input and output test point v io /2 0v device under te s t *c l = 30 pf including scope and jig capacitance
50 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 10.6 key to switching waveforms 10.7 v cc power up notes 1. reset# must be high after v cc and v io are higher than v cc minimum. 2. v cc v io ? 200 mv during power-up. 3. v cc & v io ramp rate could be non-linear 4. v cc and v io are recommended to be ramped up simultaneously. figure 10.5 v cc power-up diagram . waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) table 10.1 v cc power-up parameter description test setup speed unit t vcs v cc setup time min 300 s t vios v io setup time min 300 s t rh time between reset# (high) and ce# (low) min 200 ns v cc v io reset# t vcs t vios t rh ce# v cc min v io min v ih
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 51 data sheet (advance information) 10.8 clk characterization notes 1. dc for operations other than continuous and 16 word (32 byte) synchronous burst read. see ac characteristics table. 2. clock jitter of +-5% is permitted. figure 10.6 clk characterization 10.9 ac characteristics 10.9.1 ac characteristi cs?synchronous burst read notes 1. not 100% tested. 2. if oe# is disabled before ce# is disabled, the output goes to high-z by t oez . if ce# is disabled before oe# is disabled, the output goes to high-z by t cez . if ce# and oe# are disabled at the same time, the output goes to high-z by t oez . 3. avd can not be low for 2 subsequent clk cycles. parameter description 104 mhz unit f clk clk frequency max 104 (2) mhz min dc (1) t clk clk period min 9.6 ns t cl /t ch clk low/high time min 0.40 t clk ns t clk t cl t ch clk parameter (notes) symbol 66 83 104 unit clock frequency clk min dc (0) for operations other than continuous and 32 byte synchronous burst. 120 in 32 byte burst 1000 in continuous burst khz clock cycle t clk min 15 12 9.6 ns clk rise time t clkr max 3.0 2.5 1.92 ns clk fall time t clkf clk high or low time t clkh/l min 6 5 4 ns internal access time t ia max 75 ns burst access time valid clock to output delay t bacc max 11.2 9 7.6 ns avd# setup time to clk t avds min 4 ns avd# hold time from clk t avdh min 3 ns address setup time to clk t acs min 4 ns address hold time from clk t ach min 5 ns data hold time from next clock cycle t bdh min 3 2 ns output enable to data t oe max 15 ns ce# disable to output high z (2) t cez max 10 ns oe# disable to output high z (2) t oez max 10 ns ce# setup time to clk t ces min 4 ns clk to rdy valid t racc max 11.2 9 7.6 ns ce# low to rdy valid t cr max 10 ns avd# pulse width t avdp min 6 ns
52 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) figure 10.7 synchronous read mode 10.9.2 ac characteristics?asynchronous read notes 1. not 100% tested. 2. if oe# is disabled before ce# is disabled, the output goes to high-z by t oez . if ce# is disabled before oe# is disabled, the output goes to high-z by t cez . if ce# and oe# are disabled at the same time, the output goes to high-z by t oez . dc dd oe# a/dq15 ? a/dq0 am a x ? a16 ac avd# rdy clk ce# t ce s t ac s t avd s t avdp t ach t oe t bdh de db 7 cycle s for initi a l a cce ss i s s hown as a n ill us tr a tion. hi-z t racc 12 3 4567 t bacc t cr t ia ac t avdh parameter symbol min max unit access time from ce# low t ce ?80 ns asynchronous access time from address valid t acc ?80 read cycle time t rc 80 ? avd# low time t avdp 6? address setup to rising edge of avd# t aavds 4? address hold from rising edge of avd# t aavdh 3.5 ? output enable to output valid t oe ?15 ce# setup to avd# falling edge t cas 0? ce# disable to output & rdy high z (note 1) t cez ?10 oe# disable to output high z (note 1) t oez ?10 avd# high to oe# low t avdo 4? ce# low to rdy valid t cr ?10 we# disable to avd# enable t wea 9.6 ? we# disable to oe# enable t oeh 4?
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 53 data sheet (advance information) figure 10.8 asynchronous mode read notes 1. avd# transition occurs after ce# is driven to low and valid address transition occurs before avd# is driven to low. 2. va = valid read address, rd = read data. t ce we# amax ? a16 ce# oe# valid rd t acc t oeh t oe a/dq15 ? a/dq0 t oez t aavdh t avdp t aavds avd# ra ra hi-z hi-z rdy t cr t cez t cas
54 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 10.9.3 ac characteristi cs?erase/program timing notes 1. sampled, not 100% tested. figure 10.9 asynchronous program operation timings parameter symbol min typ max unit we# cycle time (1) t wc 60 ? ? ns avd# low pulse width t avdp 6??ns address setup to rising edge of avd# t aavds 4??ns address hold from rising edge of avd# t aavdh 3.5 ? ? ns read recovery time before write t ghwl 0??ns data setup to rising edge of we# t ds 20 ? ? ns data hold from rising edge of we# t dh 0??ns ce# setup to falling edge of we# t cs 4??ns ce# hold from rising edge of we# t ch 0 ? ? ns we# pulse width t wp 25 ? ? ns we# pulse width high t wph 20 ? ? ns latency between read and write operations t srw 0??ns avd# disable to we# disable t vlwh 23.5 ? ? ns we# disable to avd# enable t wea 9.6 ? ? ns ce# low to rdy valid t cr ? ? 10 ns ce# disable to output high z t cez ? ? 10 ns oe# disable to we# enable t weh 4 ? ? ns erase suspend latency t esl ? ? 30 s program suspend latency t psl ? ? 30 s erase resume to erase suspend t ers 30 ? ? s program resume to program suspend t prs 30 ? ? s oe# ce# avd# we# clk v cc t aavd s t wp t aavdh t wc t wph pa t c s t dh t ch 70h s t a t us ba progr a m comm a nd s e qu ence (l as t two cycle s )re a d s t a t us d a t a t d s v ih v il t avdp pd 29h t ca s a/dq15? a/dq0 am a x? a16 t vlwh ba(555h) s a(555h) ba(555h) pa ba s a(555h) t vc s + t rh
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 55 data sheet (advance information) 10.9.4 hardware reset (reset#) figure 10.10 reset timings figure 10.11 latency with boundary crossing notes 1. rdy active with data (cr.8 = 0 in the configuration register). 2. rdy active one clock cycle before data (cr.8 = 1 in the configuration register). 3. figure shows the device not crossing a bank in the process of performing an erase or program. table 10.2 warm-reset parameter description all speed options unit jedec std t rp reset# pulse width min 50 ns t rh reset high time before read min 200 ns t rph reset# low to ce# low min 10 us re s et# t rp t rph ce#, oe# t rh clk addre ss (hex) d124 d125 d126 d127 d12 8 d129 d1 3 0 ( s t a y s high) avd# rdy (note 1) d a t a oe#, ce# ( s t a y s low) addre ss b o u nd a ry occ u r s every 12 8 word s , b eginning a t a ddre ss 00007fh: (0000ffh, 00017fh, etc.) addre ss 000000h i s a l s o a b o u nd a ry cro ss ing. 7c 7d 7e 7f 7f 8 0 8 1 8 2 83 l a tency rdy (note 2) l a tency t racc t racc t racc t racc
56 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) figure 10.12 latency with boundary crossing into bank performing embedded operation notes 1. rdy active with data (cr.8 = 0 in the configuration register). 2. rdy active one clock cycle before data (cr.8 = 1 in the configuration register). 3. figure shows the device crossing a bank in the process of performing an erase or program. clk addre ss (hex) d124 d125 d126 d127 00h ( s t a y s high) avd# rdy (note 1) d a t a oe#, ce# ( s t a y s low) addre ss b o u nd a ry occ u r s every 12 8 word s , b eginning a t a ddre ss 00007fh: (0000ffh, 00017fh, etc.) addre ss 000000h i s a l s o a b o u nd a ry cro ss ing. 7c 7d 7e 7f 7f 8 0 8 1 8 2 83 rdy (note 2) t racc t racc 00h 00h 00h
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 57 data sheet (advance information) 10.9.5 wait state configur ation register setup figure 10.13 example of programmable wait states configuration register programmable wait states cr.14 cr.13 cr.12 cr.11 0000 = initial data is valid on the reserved rising clk edge after addresses are latched 0001 = 3rd 0010 = 4th 0011 = 5th 0100 = 6th 0101 = 7th 0110 = 8th 0111 = 9th 1000 = 10th . . . . . . 1011 = 13th 1100 = reserved 1111 = data avd# oe# clk 1 2345 d0 d1 0 6 1 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data total number of clock edges following addresses being latched 24 567
58 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) figure 10.14 back-to-back read/write cycle timings note breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the program or erase operation in the busy bank. the system should read status twice to ensure valid information. oe# ce# we# t oez d a t a addre ss e s avd# wd 25h ra wa t wc t d s t dh t rc t rc t oe t aavd s t aavdh t acc t oeh t wp t ghwl t wc t s r/w l as t cycle in progr a m or s ector er as e comm a nd s e qu ence re a d s t a t us ( a t le as t two cycle s ) in sa me ba nk a nd/or a rr a y d a t a from other ba nk begin a nother write or progr a m comm a nd s e qu ence rd ra s a(555h) rd t wph
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 59 data sheet (advance information) 10.9.6 erase and programming performance notes 1. typical program and erase times assume the following conditions: 25c, 1.8 v v cc , 10,000 cycles. additionally, programming typically assumes a checkerboard pattern. 2. under worst case conditions of 90c, v cc = 1.70 v, 100,000 cycles. 3. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 4. system-level overhead is the time required to exec ute the bus-cycle sequence for the program command. see table 11.1 on page 60 for further information on command definitions. 5. the device has a minimum erase and pr ogram cycle endurance of 10,000 cycles. 6. the first value excludes pre-programming time, while the second value is inclusive of pre-programming time for the ffffh patt ern, with status polling rate as 400 ns. 7. the erase time is calculated fr om the time of issuing erase command to the completion of erase operation (indicated by status register) parameter typ (note 1) max (note 2) unit comments sector erase time 128 kbyte v cc 0.8/1.3 (note 6) 3.5/5.5 s (note 3) 32 kbyte v cc 0.35/0.6 (note 6) 2.0/3.5 128 kbyte v pp 0.8/1.3 (note 6) 3.5/5.5 32 kbyte v pp 0.35/0.6 (note 6) 2.0/3.5 chip erase time (note 7) v cc (note 6) 78/126 (128 mbit) 155/251 (256 mbit) 154/250 (128 mbit) 308/500 (256 mbit) v pp (note 6) 78/126 (128 mbit) 155/251 (256 mbit) 154/250 (128 mbit) 308/500 (256 mbit) single word program time (using program buffer) v cc 170 800 s excludes system level overhead (note 4) effective word programming time using program write buffer v cc 9.4 94 v pp 4.8 48 total 32-word buffer programming time v cc 300 3000 v pp 154 1540 chip programming time (using 32 word buffer) v cc 79 (128 mbit) 157 (256 mbit) 157 (128 mbit) 315 (256 mbit) s excludes system level overhead (note 4) v pp 40 (128 mbit) 80 (256 mbit) 80 (128 mbit) 160 (256 mbit) erase suspend/erase resume (t esl )30s program suspend/program resume (t psl ) 30 s blank check 1ms
60 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 11. appendix this section contains information relating to softw are control or interfacing with the flash device. 11.1 command definitions all values are in hexadecimal. the s29vs-r family of devices are 16-bit word addre ss oriented. most system address buses, regardless of data bus size, are byte orie nted. it is common practice for system designers to shift the address busses. that is, flash address a0 is connected to system address a1, etc. to accommodate the system desi gners, addresses are listed in both wo rd address and byte address where applicable. the flash address (word) is listed above the system address (byte). table 11.1 command definitions (sheet 1 of 2) command sequence cycles bus cycles (notes 1 ? 4 ) first second third fourth addr data addr data addr data addr data read ra rd reset 1 x f0 write buffer load (8) 4-35 (sa) 555 (sa) aaa 25 (sa) 2aa (sa) 554 wc (sa) pa (11) pd pa (12) pd buffer to flash 1 (sa) 555 (sa) aaa 29 chip erase 2 (sa) 555 (sa) aaa 80 (sa) 2aa (sa) 554 10 sector erase 2 (sa) 555 (sa) aaa 80 (sa) 2aa (sa) 554 30 read status register 2 (sa) 555 (sa) aaa 70 (sa) rr clear status register 1 (sa) 555 (sa) aaa 71 program suspend (5) 1 xxx 51 program resume (5) 1 (sa) 000 50 erase suspend (6) 1 xxx b0 erase resume (6) 1 (sa) 000 30 blank check 1 (sa) 555 (sa) aaa 33 sector lock/unlock 3 555 aaa 60 2aa 554 60 sla 60 sector lock range 4 555 aaa 60 2aa 554 60 sla 61 sla 61 id/cfi command definitions id/cfi id/cfi entry (7) (10) 1 (sa) x55 (sa) xaa 90 or 98 id/cfi read 1 (sa) ra data id/cfi exit 1 xxx fo configuration command definitions configuration register configuration register entry (7) (10) 1 (sa) 555 (sa) aaa d0 write buffer load 3 (sa) 555 (sa) aaa 25 (sa) 2aa (sa) 554 0 (sa) x00 pd buffer to flash (configuration register) 1 (sa) 555 (sa) aaa 29 configuration register read 1 (sa) x00 rr configuration register exit 1 xxx fo
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 61 data sheet (advance information) legend x = don?t care ra = address of the location to be read. rd = read data from location ra during read operation. rr = read register value pa = address of the memory location to be programmed. pd = data to be programmed at location pa. ba = address bits sufficient to select a bank sa = address bits suffic ient to select a sector sla = sector lock address wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes 1. see section 7., device operations on page 23 for description of bus operations. 2. except for the following, all bus cycles are write cycle: r ead cycle during read, id/cfi read (manufacturing id, device id, i ndicator bits), configuration register read, secure silicon region read, ssr lock read, and 2nd cycle of status register read 3. data bits dq15?dq8 are don?t care in command sequences, except for rd, pd, and wd. 4. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data 5. the program resume command is valid only during the program suspend mode/state. 6. the erase resume command is valid only during the erase suspend mode/state. 7. command is valid when all banks are ready to read array data. 8. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. 9. v pp must be at v hh during the entire operation of this command 10. entry commands are needed to enter a specific mode to enable instructions only available within that mode. 11. must be the lowest word address of the words being programmed within the 32 word write buffer page. this is not necessarily the lowest address of the page. data words are loaded into the write page buffer in sequential order from lowest to highest address. 12. subsequent addresses must fall within the same sector and page as the initial starting address. ssr lock command definitions ssr lock ssr lock entry (7) (10) 1 (sa) 555 (sa) aaa 40 write buffer load (8) 3 (sa) 555 (sa) aaa 25 (sa) 2aa (sa) 554 0 (sa) 00 pd buffer to flash 1 (sa) 555 (sa) aaa 29 ssr lock read 1 (sa) xxx rr ssr lock exit 1 xxx f0 secure silicon region command definitions secure silicon region secure silicon region entry (7) (10) 1 (sa) 555 (sa) aaa 88 write buffer load (8) 4-35 (sa) 555 (sa) aaa 25 (sa) 2aa (sa) 554 wc (sa) pa pd (sa) pa pd buffer to flash 1 (sa) 555 (sa) aaa 29 secure silicon region read 1 (sa) ra rd secure silicon region exit 1 xxx f0 table 11.1 command definitions (sheet 2 of 2) command sequence cycles bus cycles (notes 1 ? 4 ) first second third fourth addr data addr data addr data addr data
62 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 11.2 device id and common flash memory interface address map the device id fields occupy the first 32 bytes of addr ess space followed by the common flash interface data structure. the common flash interfac e (cfi) specification defines a stand ardized data structure containing device specific parameter, structure, and feature set information, which allows vendor-specified software algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back-ward-compati ble for the specified flash device families. flash driver software can be standardiz ed for long-term compatibility. this device enters the id/cfi mode when the system writes the id/cfi query command, 90h or 98h, to address (sa)55h any time all banks are in read mode (the cu is in idle state). the system can then read id and cfi information at the addresses, within the selected sector, given in the following tables. to terminate reading id/cfi, the system must write the reset command. table 11.2 id/cfi data (sheet 1 of 5) word offset address byte offset address data description vs256r/xs256r vs128r/xs128r device identification (sa) + 00h (sa) + 00h 0001h spansion manufacturer id (sa) + 01h (sa) + 02h 007eh (top/bottom) 007eh (top/bottom) device id, word 1 extended id address code. indicates an extended two byte device id is located at byte address 1ch and 1eh. (sa) + 02h (sa) + 04h reserved reserved (sa) + 03h (sa) + 06h 0000h (top/bottom) revision id (sa) + 04h (sa) + 08h reserved reserved (sa) + 05h (sa) + 0ah reserved reserved (sa) + 06h (sa) + 0ch 0010h id version (sa) + 07h (sa) + 0eh dq15 - dq8 = reserved dq7 - factory lock bit: 1 = locked; 0 = not locked dq6 - customer lock bit: 1 = locked; 0 = not locked dq5 - dq0 = reserved indicator bits (sa) + 08h (sa) + 10h reserved reserved (sa) + 09h (sa) + 12h reserved reserved (sa) + 0ah (sa) + 14h reserved reserved (sa) + 0bh (sa) + 16h reserved reserved (sa) + 0ch (sa) + 18h 0 5 h bit 0 - status register support 1 = status register supported 0 = status register not supported bit 1 - dq polling support 1 = dq bits polling supported 0 = dq bits polling not supported bit 3-2 - command set support 11 = reserved 10 = reserved 01 = reduced command set 00 = old command set bit 4- f - reserved lower software bits (sa) + 0dh (sa) + 1ah reserved upper software bits reserved (sa) + 0eh (sa) + 1ch 0064h/top; 0066h/bottom 0063h/top; 0065h/bottom high order device id, word 2 (sa) + 0fh (sa) + 1eh 0001h (top/bottom) 0001h (top/bottom) low order device id, word 3
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 63 data sheet (advance information) cfi cfi query identification string (sa) + 10h (sa) + 20h 0051h query unique ascii string ?qry? (sa) + 11h (sa) + 22h 0052h (sa) + 12h (sa) + 24h 0059h (sa) + 13h (sa) + 26h 0002h primary algorithm command set (spansion = 0002h) (sa) + 14h (sa) + 28h 0000h (sa) + 15h (sa) + 2ah 0040h address for primary extended table (sa) + 16h (sa) + 2ch 0000h (sa) + 17h (sa) + 2eh 0000h alternate algorithm command set (00h = none exists) (sa) + 18h (sa) + 30h 0000h (sa) + 19h (sa) + 32h 0000h address for secondary algorithm extended query table (00h = none exists) (sa) + 1ah (sa) + 34h 0000h common flash interface system interface string (sa) + 1bh (sa) + 36h 0017h v cc logic supply minimum program/erase or write voltage d7-d4: volt d3-d0: 100 millivolt (sa) + 1ch (sa) + 38h 0019h v cc logic supply maximum program/erase or write voltage d7-d4: volt d3-d0: 100 millivolt (sa) + 1dh (sa) + 3ah 0000h v pp [programming] supply minimum program/erase voltage (00h = no v pp pin present) (sa) + 1eh (sa) + 3ch 0000h v pp [programming] supply maximum program/erase voltage (00h = no v pp pin present) (sa) + 1fh (sa) + 3eh 0008h typical word programming time per single word 2 n s (e.g. < or = 32 s) (sa) + 20h (sa) + 40h 0009h typical program time for programming the complete buffer 2 n s (e.g. < or = 256 s) (00h = not supported) (sa) + 21h (sa) + 42h 000ah typical time for sector erase 2 n ms (sa) + 22h (sa) + 44h 0012h 0011h typical time for full chip erase 2 n s (00h = not supported) (sa) + 23h (sa) + 46h 0003h max. program time per single word [2 n times typical value] (sa) + 24h (sa) + 48h 0003h max. program time using buffer [2 n times typical value] (sa) + 25h (sa) + 4ah 0003h max. time for sector erase [2 n times typical value] (sa) + 26h (sa) + 4ch 0003h max. time for full chip erase [2 n times typical value] (00h = not supported) table 11.2 id/cfi data (sheet 2 of 5) word offset address byte offset address data description vs256r/xs256r vs128r/xs128r
64 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) common flash interface device geometry definition (sa) + 27h (sa) + 4eh 0019h 0018h device size = 2 n byte (sa) + 28h (sa) + 50h 0001h flash device interface 0h = x8 1h = x16 2h = x8/x16 3h = x32 [lower byte] (sa) + 29h (sa) + 52h 0000h [upper byte] (00h = not supported) (sa) + 2ah (sa) + 54h 0006h max. number of bytes in multi-byte buffer write = 2 n [lower byte] (sa) + 2bh (sa) + 56h 0000h [upper byte] (00h = not supported) (sa) + 2ch (sa) + 58h 0002h number of erase block regions within device (number of regions within the device containing one or more contiguous erase blocks of the same size) (sa) + 2dh (sa) + 5ah 00feh (top boot) 007eh (top boot) erase block region 1 information [lower byte] - number of erase sectors of identical size within the erase block region. 00h = 1 sector; 01h = 2 sectors 02h = 3 sectors 03h = 4 sectors 0003h (bottom boot) 0003h (bottom boot) (sa) + 2eh (sa) + 5ch 0000h [upper byte] (sa) + 2fh (sa) + 5eh 0000h (top boot) [lower byte] - sector size in bytes divided by 256 (n [bytes]h = sector size / 256) 0080h (bottom boot) (sa) + 30h (sa) + 60h 0002h (top boot) [upper byte] 0000h (bottom boot) (sa) + 31h (sa) + 62h 0003h (top boot) 0003h (top boot) erase block region 2 information 00feh (bottom boot) 007eh (bottom boot) (sa) + 32h (sa) + 64h 0000h [upper byte] (sa) + 33h (sa) + 66h 0080h (top boot) [lower byte] - sector size in bytes divided by 256 (n [bytes]h = sector size / 256) 0000h (bottom boot) (sa) + 34h (sa) + 68h 0000h (top boot) [upper byte] 0002h (bottom boot) table 11.2 id/cfi data (sheet 3 of 5) word offset address byte offset address data description vs256r/xs256r vs128r/xs128r
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 65 data sheet (advance information) common flash interface primary algorithm-specific extended query (sa) + 40h (sa) + 80h 0050h query unique ascii string ?pri? (sa) + 41h (sa) + 82h 0052h (sa) + 42h (sa) + 84h 0049h (sa) + 43h (sa) + 86h 0031h major cfi version number, ascii (sa) + 44h (sa) + 88h 0034h minor cfi version number, ascii (sa) + 45h (sa) + 8ah 0020h address sensitive unlock (bits 1-0): 00b = required 01b = not required process technology (bits 5-2) 0011b = 130 nm floating-gate technology 0100b = 110 nm mirrorbit technology 0101b = 90 nm floating-gate technology 0110b = 90 nm mirrorbit technology 1000b = 65 nm mirrorbit technology (sa) + 46h (sa) + 8ch 0002h erase suspend 0= not supported 1 = to read only 2 = to read & write (sa) + 47h (sa) + 8eh 0001h sector protection per group 0 = not supported x = number of sectors in per group (sa) + 48h (sa) + 90h 0000h sector temporary unprotect 00h = not supported 01h = supported (sa) + 49h (sa) + 92h 0009h sector protect/unprotect scheme 08h = advanced sector protection 09h = single-sector lock + sector lock range (sa) + 4ah (sa) + 94h 00e0h 0070h simultaneous operations number of sectors in all banks except boot bank (sa) + 4bh (sa) + 96h 0001h burst mode type 00h = not supported 01h = supported (sa) + 4ch (sa) + 98h 0000h page mode type 00h = not supported 01h = 4-word page 02h = 8-word page 04h = 16-word page (sa) + 4dh (sa) + 9ah 0085h v pp (acceleration) supply minimum 00h = not supported d7-d4: volt d3-d0: 100 millivolt (sa) + 4eh (sa) + 9ch 0095h v pp (acceleration) supply maximum 00h = not supported d7-d4: volt d3-d0: 100 millivolt (sa) + 4fh (sa) + 9eh 03h (top boot) 02h (bottom boot) top/bottom sector flag 00h = uniform 01h = dual boot 02h = bottom boot 03h = top boot (sa) + 50h (sa) + a0h 0001h program suspend 00h = not supported 01h= supported table 11.2 id/cfi data (sheet 4 of 5) word offset address byte offset address data description vs256r/xs256r vs128r/xs128r
66 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) common flash interface (sa) + 51h (sa) + a2h 0000h unlock bypass 00h = not supported 01h = supported (sa) + 52h (sa) + a4h 0007h secure silicon region (customer ssr area) size 2 n bytes (sa) + 53h (sa) + a6h 000eh hardware reset low time-out until reset is completed during an embedded algorithm - maximum 2 n ns (e.g. 10 s => n = e) (sa) + 54h (sa) + a8h 000eh hardware reset low time-out until reset is completed not during an embedded algorithm - maximum 2 n ns (e.g. 10 s => n = e) (sa) + 55h (sa) + aah 0008h erase suspend time-out maximum 2 n ns (sa) + 56h (sa) + ach 0008h program suspend time-out maximum 2 n ns (sa) + 57h (sa) + aeh 0008h bank organization: x= number of banks common flash interface (sa) + 58h (sa) + b0h 0020h (top boot) 0010h (top boot) bank 0 region information. x= number of sectors in bank 0023h (bottom boot) 0013h (bottom boot) (sa) + 59h (sa) + b2h 0020h 0010h bank 1 region information. x= number of sectors in bank (sa) + 5ah (sa) + b4h 0020h 0010h bank 2 region information. x= number of sectors in bank (sa) + 5bh (sa) + b6h 0020h 0010h bank 3 region information. x= number of sectors in bank (sa) + 5ch (sa) + b8h 0020h 0010h bank 4 region information. x= number of sectors in bank (sa) + 5dh (sa) + bah 0020h 0010h bank 5 region information. x= number of sectors in bank (sa) + 5eh (sa) + bch 0020h 0010h bank 6 region information. x= number of sectors in bank (sa) + 5fh (sa) + beh 0020h (bottom boot) 0010h (bottom boot) bank 7 region information. x= number of sectors in bank 0023h (top boot) 0013h (top boot) table 11.2 id/cfi data (sheet 5 of 5) word offset address byte offset address data description vs256r/xs256r vs128r/xs128r
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 67 data sheet (advance information) figure 11.1 asynchronous read - aadm interface figure 11.2 asynchronous read followed by read - aadm interface add-hi add-low d a t a t cr t cr t cez t oez t acc t acc t ce t oe t avdp t avdp t avdp t aavdh t aavdh t aavd s t aavd s t aavdh t aavdh t aavd s t aavd s t ca s oe# en ab le s d a t a o u tp u t only a fter the addre ss -low cycle in which avd# i s low a nd oe# i s high oe# i s ignored a fter oe# ret u rn s high b etween a cce ss e s u ntil the next addre ss -low i s received oe# low with avd# low s ign a l s the pre s ence of addre ss -high. the addre ss -high cycle i s option a l. when the high p a rt of a ddre ss doe s not ch a nge only the addre ss -low cycle i s needed. ce# avd# oe# we# a/dq15- a/dq0 rdy ah al d ah al d t cez t cr t oez t cez t acc t acc t oez t acc t acc t ce t oe t aavdh t aavd s t aavdh t aavd s t wea t oeh t avdo t avdo t aavdh t aavd s t avdp t t ca s clk m a y b e a t v il or v ih or toggle clk ce# avd# oe# we# a/dq15- a/dq0 rdy t oe
68 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) figure 11.3 asynchronous read followed by write - aadm interface figure 11.4 asynchronous write - aadm interface ah al d ah al d t cez t cr t cez t oez t ce t acc t acc t oe t dh t d s t aavdh t aavd s t ch t wc t wp t c s t vlwh t wph t wea t oeh t aavdh t aavd s t avdo t aavdh t aavd s t avdp t ca s clk m a y b e a t v il or v ih or toggle clk ce# avd# oe# we# a/dq15- a/dq0 rdy add-high add-low d a t a t cez t cr t dh t d s t aavdh t aavdh t aavd s t aavd s t ch t vlwh t wc t wp t c s t wph t wea t aavdh t aavd s t avdp t avdp t avdp t ca s oe# low with avd# low s ign a l s the pre s ence of addre ss -high. the addre ss -high cycle i s option a l. when the high p a rt of a ddre ss doe s not ch a nge only the addre ss -low cycle i s needed. oe# en ab le s d a t a o u tp u t only a fter the addre ss -low cycle in which avd# i s low a nd oe# i s high. oe# i s ignored a fter oe# ret u rn s high b etween a cce ss e s u ntil the next addre ss -low i s received. clk m a y b e a t v il or v ih or toggle clk ce# avd# oe# we# a/dq15- a/dq0 rdy
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 69 data sheet (advance information) figure 11.5 asynchronous write followed by read - aadm interface figure 11.6 asynchronous write followed by write - aadm interface ah al d ah al d t cez t cr t cez t oez t acc t acc t oe t dh t d s t aavdh t aavd s t oeh t vlwh t ch t wc t wp t c s t wph t wea t avdo t aavdh t aavd s t avdp t ca s clk ce# avd# oe# we# a/dq15- a/dq0 rdy clk m a y b e a t v il or v ih or toggle ah al d ah al d t cez t cr t dh t aavdh t d s t aavdh t aavd s t aavd s t vlwh t ch t wc t wp t vlwh t wph t wp t wea t c s t aavdh t aavd s t aavdh t aavd s t avdp t ca s clk m a y b e a t v il or v ih or toggle clk ce# avd# oe# we# a/dq15- a/dq0 rdy t d s t dh
70 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) figure 11.7 synchronous read wrapped burst address low only - aadm interface figure 11.8 synchronous read continuous burst - aadm interface ah al al t racc t racc t racc t cez t racc t racc t racc t racc t cr t oez t bdh t bacc t oe t oez t bdh t bacc t oe t ach t ac s t avdh t avd s t avdh t avdp t avd s t ce s t ia oe# en ab le s d a t a o u tp u t only a fter the addre ss -low cycle in which avd# i s low a nd oe# i s high. oe# i s ignored a fter oe# ret u rn s high b etween a cce ss e s u ntil the next addre ss -low i s received. oe# low with avd# low s ign a l s the pre s ence of addre ss -high. the addre ss -high cycle i s option a l. when the high p a rt of a ddre ss doe s not ch a nge only the addre ss -low cycle i s needed. addre ss -low only cycle clk ce# avd# oe# we# a/dq15 - a/dq0 rdy(with d a t a ) rdy( b efore d a t a ) t racc t racc t racc t cez t racc t racc t racc t cr t oez t bacc t bdh t bacc t oe t ach t ac s t avdh t avd s t avdh t avdp t avd s t ce s t ia t ia in contin u o us bu r s t, w a it s t a te s e qua l to the intern a l a cce ss time a re in s erted b etween the end of one c a che line a nd the s t a rt of the next c a che line clk ce# avd# oe# we# a/dq15-a/dq0 rdy(with d a t a ) rdy( b efore d a t a )
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 71 data sheet (advance information) figure 11.9 synchronous read wrapped burst - aadm interface figure 11.10 synchronous write followed by read burst - aadm interface ah al t cez t racc t cez t racc t racc t cr t oez t bdh t bacc t oe t ach t ac s t avdh t avd s t avdh t avdp t avd s t ce s t ia 15 initi a l a cce ss cycle s s etting s hown. t ia me asu red from clk ri s ing edge d u ring avd# low to clk ri s ing edge a t b eginning of fir s t d a t a o u t. oe# en ab le s d a t a o u tp u t only a fter the addre ss -low cycle in which avd# i s low a nd oe# i s high. oe# i s ignored a fter oe# ret u rn s high b etween a cce ss e s u ntil the next addre ss -low i s received. oe# low with avd# low s ign a l s the pre s ence of addre ss -high. the addre ss -high cycle i s option a l. when the high p a rt of a ddre ss doe s not ch a nge only the addre ss -low cycle i s needed. clk ce# avd# oe# we# a/dq15-a/dq0 rdy(with d a t a ) rdy( b efore d a t a ) ah al ah al t racc t racc t racc t cez t racc t racc t racc t racc t cr t oez t bacc t oe a s ic_t co t oez t bdh t bacc t oe t ach t ac s t avdh t avd s t avdh t avdp t avd s t ce s t ia t ia clk ce# avd# oe# we# a/dq15 - a/dq0 rdy(with d a t a ) rdy( b efore d a t a )
72 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) figure 11.11 synchronous read followed by write - aadm interface figure 11.12 synchronous write followed by read burst - aadm interface ah al ah al write d a t a t racc t racc t racc t cez t racc t racc t racc t racc t cr t oez t bacc t bdh t bacc t oe t dh t d s t ach t ac s t ch t vlwh t wp t oeh t wc t wph t wea t avdp t avdh t avdp t avd s t ce s t ia clk ce# avd# oe# we# a/dq15-a/dq0 rdy(with d a t a ) rdy( b efore d a t a ) ah al write d a t a ah al t racc t racc t cr t cez t racc t racc t racc t cr t oez t bacc t bdh t bacc t oe t dh t d s t aavdh t aavd s t oeh t vlwh t wp# t wc t wph t wea t avdh t ce s t avd s t ca s t avdp t ia addre ss -high cycle s option a l addre ss -high cycle s option a l clk ce# avd# oe# we# a/dq15-a/dq0 rdy(with d a t a ) rdy( b efore d a t a )
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 73 data sheet (advance information) figure 11.13 synchronous write followed by write - aadm interface ah al write d a t a ah al write d a t a t cez t racc t racc t racc t cr t dh t d s t aavdh t aavd s t dh t d s t aavdh t aavd s t vlwh t ch t wp t vlwh t wc t wph t wea t wc t wp t c s t aavdh t aavd s t aavdh t aavd s t avdp t ca s clk ce# avd# oe# we# a/dq15- a/dq0 rdy
74 s29vs/xs-r mirrorbit ? flash family s29vs_xs-r_00_03 september 12, 2008 data sheet (advance information) 12. revision history section description revision 01 (may 15, 2008) initial release revision 02 (august 1, 2008) dc characteristics changed some values in the cmos compatible table device id and common flash memory interface address map changed some values in the id/cfi data table memory address map added memory address map revision 03 (september 12, 2008) physical dimensions/connection diagrams updated ball positions
september 12, 2008 s29vs_xs-r_00_03 s29vs/xs-r mirrorbit ? flash family 75 data sheet (advance information) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2008 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , ornand2 ? , hd-sim ? , ecoram ? and combinations thereof, are trademarks of spansion llc in the us and other countries. other names used are for informational purposes only and may be tr ademarks of their respective owners.

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